
91
8048C鈥揂VR鈥�02/12
ATtiny43U
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCFnx, with Prescaler (f
clk_I/O/8)
and fast PWM mode where OCRnA is TOP.
Figure 12-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-
caler (f
clk_I/O/8)
OCFnx
OCRnx
TCNTn
OCRnx Value
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
clk
I/O
clk
Tn
(clk
I/O/8)
OCFnx
OCRnx
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O/8)