參數(shù)資料
型號: PIC16LF88-I/ML
廠商: Microchip Technology
文件頁數(shù): 22/200頁
文件大?。?/td> 0K
描述: IC MCU FLASH 4KX14 EEPROM 28QFN
產(chǎn)品培訓模塊: Asynchronous Stimulus
標準包裝: 61
系列: PIC® 16F
核心處理器: PIC
芯體尺寸: 8-位
速度: 10MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 7KB(4K x 14)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 368 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 7x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 640 (CN2011-ZH PDF)
118
8008H–AVR–04/11
ATtiny48/88
Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the sys-
tem clock frequency (f
ExtClk < fclk_I/O/2) given a 50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling fre-
quency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source tolerances, it is recommended that maximum fre-
quency of an external clock source is less than f
clk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1
Note:
1. The synchronization logic on the input pins (
T1/T0) is shown in Figure 13-1.
13.4
Register Description
13.4.1
GTCCR – General Timer/Counter Control Register
Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
PSRSYNC
Clear
clk
T1
clk
T0
T1
T0
clk
I/O
Synchronization
Bit
76543
2
1
0
TSM
––––
PSRSYNC
GTCCR
Read/Write
R/W
R
RRRR
R
R/W
Initial Value
00000
0
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