參數(shù)資料
型號: PIC17C766T-33/PT
廠商: Microchip Technology
文件頁數(shù): 34/159頁
文件大?。?/td> 0K
描述: IC MCU OTP 16KX16 A/D 80TQFP
標準包裝: 1,200
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 33MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 66
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: OTP
RAM 容量: 902 x 8
電壓 - 電源 (Vcc/Vdd): 4.5 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 16x10b
振蕩器型: 外部
工作溫度: 0°C ~ 70°C
封裝/外殼: 80-TQFP
包裝: 帶卷 (TR)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
Section 5 Exception Handling
R01UH0025EJ0300 Rev. 3.00
Page 97 of 1336
Sep 24, 2010
SH7261 Group
5.1.2
Exception Handling Operations
The exception handling sources are detected and begin processing according to the timing shown
in table 5.2.
Table 5.2
Timing of Exception Source Detection and Start of Exception Handling
Exception
Source
Timing of Source Detection and Start of Handling
Power-on reset
Starts when the
RES pin changes from low to high, when the
H-UDI reset negate command is set after the H-UDI reset
assert command has been set, or when the WDT overflows.
Reset
Manual reset
Starts when the
MRES pin changes from low to high or when
the WDT overflows.
Address error
Bus error
Interrupts
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Bank underflow
Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
Register bank
error
Bank overflow
In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the INTC is 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
Trap instruction
Starts from the execution of a TRAPA instruction.
General illegal
instructions
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot).
Slot illegal
instructions
Starts from the decoding of undefined code placed immediately
after a delayed branch instruction (delay slot), of instructions
that rewrite the PC, of 32-bit instructions, of the RESBANK
instruction, of the DIVS instruction, or of the DIVU instruction.
Integer division
exceptions
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by
1.
Instructions
FPU exceptions
Exception handling starts triggered by disabled operation
exception of floating-point operation instruction (IEEE754
standard), division exception by zero, overflow, underflow, or
imprecise exception. Setting the QIS bit in FPSCR or inputting
qNaN as well as
±∞ as the floating-point operation instruction
source also starts exception handling.
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