- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄3895 > PIC17LC42A-08/L (Microchip Technology)IC MCU OTP 2KX16 PWM 44PLCC PDF資料下載
參數(shù)資料
| 型號： | PIC17LC42A-08/L |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 235/241頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU OTP 2KX16 PWM 44PLCC |
| 標準包裝： | 27 |
| 系列： | PIC® 17C |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 8MHz |
| 連通性： | UART/USART |
| 外圍設(shè)備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 33 |
| 程序存儲器容量： | 4KB（2K x 16） |
| 程序存儲器類型： | OTP |
| RAM 容量： | 232 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.5 V ~ 6 V |
| 振蕩器型： | 外部 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁第234頁當前第235頁第236頁第237頁第238頁第239頁第240頁第241頁
1996 Microchip Technology Inc.
DS30412C-page 93
PIC17C4X
13.3
USART Synchronous Master Mode
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous
mode
is
entered
by
setting
the
SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to congure the RA5 and RA4 I/O ports
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting the CSRC (TXSTA<7>) bit.
13.3.1
USART SYNCHRONOUS MASTER
TRANSMISSION
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), TXREG
is empty and the TXIF (PIR<1>) bit is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE
bit (PIE<1>). TXIF will be set regardless of the state of
bit TXIE and cannot be cleared in software. It will reset
only when new data is loaded into TXREG. While TXIF
indicates the status of TXREG, TRMT (TXSTA<1>)
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty. The TSR is not
mapped in data memory, so it is not available to the
user.
Transmission
is
enabled
by
setting
the
TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The rst data
bit will be shifted out on the next available rising edge
of the clock on the RA5/TX/CK pin. Data out is stable
around the falling edge of the synchronous clock
(Figure 13-10). The transmission can also be started
by rst loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is rst started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to
the
TSR,
resulting
in
an
empty
TXREG.
Back-to-back transfers are possible.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RA4/RX/DT and RA5/TX/CK pins will revert to
hi-impedance. If either CREN or SREN are set during
a transmission, the transmission is aborted and the
RA4/RX/DT pin reverts to a hi-impedance state (for a
reception). The RA5/TX/CK pin will remain an output if
the CSRC bit is set (internal clock). The transmitter
logic is not reset, although it is disconnected from the
pins. In order to reset the transmitter, the user has to
clear the TXEN bit. If the SREN bit is set (to interrupt an
ongoing transmission and receive a single word), then
after the single word is received, SREN will be cleared
and the serial port will revert back to transmitting, since
the TXEN bit is still set. The DT line will immediately
switch from hi-impedance receive mode to transmit
and start driving. To avoid this, TXEN should be
cleared.
In
order
to
select
9-bit
transmission,
the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
2.
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
3.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
4.
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
5.
If 9-bit transmission is desired, then set the TX9
bit.
6.
Start transmission by loading data to the
TXREG register.
7.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
8.
Enable the transmission by setting TXEN.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
proper
state
when
transmit
is
re-enabled.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PIC17LC42A-08/PQ | IC MCU OTP 2KX16 PWM 44-MQFP |
| PIC17LC42A-08I/PT | IC MCU OTP 2KX16 PWM 44TQFP |
| PIC17LC42A-08I/PQ | IC MCU OTP 2KX16 PWM 44-MQFP |
| PIC17LC42A-08I/P | IC MCU OTP 2KX16 PWM 40DIP |
| PIC17LC42A-08I/L | IC MCU OTP 2KX16 PWM 44PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PIC17LC42AT-08/L | 功能描述:8位微控制器 -MCU 4KB 232 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC17LC42AT-08/PQ | 功能描述:8位微控制器 -MCU 4KB 232 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC17LC42AT-08/PT | 功能描述:8位微控制器 -MCU LOW PWR RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC17LC42AT-08I/L | 功能描述:8位微控制器 -MCU 4KB 232 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
| PIC17LC42AT-08I/PQ | 功能描述:8位微控制器 -MCU 4KB 232 RAM 33 I/O RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。