參數(shù)資料
型號(hào): PIC17LC42A-08I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 230/241頁(yè)
文件大小: 0K
描述: IC MCU OTP 2KX16 PWM 40DIP
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 17C
核心處理器: PIC
芯體尺寸: 8-位
速度: 8MHz
連通性: UART/USART
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 33
程序存儲(chǔ)器容量: 4KB(2K x 16)
程序存儲(chǔ)器類型: OTP
RAM 容量: 232 x 8
電壓 - 電源 (Vcc/Vdd): 2.5 V ~ 6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
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1996 Microchip Technology Inc.
DS30412C-page 89
PIC17C4X
13.2
USART Asynchronous Mode
In this mode, the USART uses standard nonre-
turn-to-zero (NRZ) format (one start bit, eight or nine
data bits, and one stop bit). The most common data for-
mat is 8-bits. An on-chip dedicated 8-bit baud rate gen-
erator can be used to derive standard baud rate
frequencies from the oscillator. The USART’s transmit-
ter and receiver are functionally independent but use
the same data format and baud rate. The baud rate
generator produces a clock x64 of the bit shift rate. Par-
ity is not supported by the hardware, but can be imple-
mented in software (and stored as the ninth data bit).
Asynchronous mode is stopped during SLEEP.
The asynchronous mode is selected by clearing the
SYNC bit (TXSTA<4>).
The USART Asynchronous module consists of the fol-
lowing important elements:
Baud Rate Generator
Sampling Circuit
Asynchronous Transmitter
Asynchronous Receiver
13.2.1
USART ASYNCHRONOUS TRANSMITTER
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
shift register (TSR). The shift register obtains its data
from the read/write transmit buffer (TXREG). TXREG is
loaded with data in software. The TSR is not loaded
until the stop bit has been transmitted from the previous
load. As soon as the stop bit is transmitted, the TSR is
loaded with new data from the TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one TCY at the end of the current BRG cycle), the
TXREG is empty and an interrupt bit, TXIF (PIR<1>) is
set. This interrupt can be enabled or disabled by the
TXIE bit (PIE<1>). TXIF will be set regardless of TXIE
and cannot be reset in software. It will reset only when
new data is loaded into TXREG. While TXIF indicates
the status of the TXREG, the TRMT (TXSTA<1>) bit
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty.
Note:
The TSR is not mapped in data memory,
so it is not available to the user.
Transmission
is
enabled
by
setting
the
TXEN (TXSTA<5>) bit. The actual transmission will not
occur until TXREG has been loaded with data and the
baud rate generator (BRG) has produced a shift clock
(Figure 13-5). The transmission can also be started by
rst loading TXREG and then setting TXEN. Normally
when transmission is rst started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to TSR resulting in an empty TXREG. A back-to-back
transfer is thus possible (Figure 13-6). Clearing TXEN
during a transmission will cause the transmission to be
aborted. This will reset the transmitter and the
RA5/TX/CK pin will revert to hi-impedance.
In
order
to
select
9-bit
transmission,
the
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to the
TXREG. This is because a data write to TXREG can
result in an immediate transfer of the data to the TSR
(if the TSR is empty).
Steps to follow when setting up an Asynchronous
Transmission:
1.
Initialize the SPBRG register for the appropriate
baud rate.
2.
Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3.
If interrupts are desired, then set the TXIE bit.
4.
If 9-bit transmission is desired, then set the TX9
bit.
5.
Load data to the TXREG register.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
7.
Enable the transmission by setting TXEN (starts
transmission).
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the opposite
order.
Note:
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
proper
state
when
transmit
is
re-enabled.
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