參數(shù)資料
型號(hào)： PIC18C801T-I/PT
廠商： Microchip Technology
文件頁(yè)數(shù)： 258/319頁(yè)
文件大小： 0K
描述： IC MCU ROMLESS A/D PWM 80TQFP
標(biāo)準(zhǔn)包裝： 1,200
系列： PIC® 18C
核心處理器： PIC
芯體尺寸： 8-位
速度： 25MHz
連通性： EBI/EMI，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，LVD，POR，PWM，WDT
輸入/輸出數(shù)： 37
程序存儲(chǔ)器類型： ROMless
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 12x10b
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-TQFP
包裝： 帶卷 (TR)
配用： XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
其它名稱： PIC18C801TI/PT
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2001 Microchip Technology Inc.
Advance Information
DS39541A-page 43
PIC18C601/801
4.1.2
BOOT LOADER
When configured as Program Memory, Boot RAM can
be used as a temporary “Boot Loader” for programming
purposes. If an external memory device is used as pro-
gram memory, any updates performed by the user pro-
gram will have to be performed in the “Boot RAM”,
because the user program cannot program and fetch
from external memory, simultaneously.
A typical boot loader execution and external memory
programming sequence would be as follows:
The boot loader program is transferred from the
external program memory to the last 2 banks of
data RAM by TBLRD and MOVWF instructions.
Once the “boot loader” program is loaded into
internal memory and verified, open combination
lock and set PGRM bit to configure the data RAM
into program RAM.
Jump to beginning of Boot code in Boot RAM.
Program execution begins in Boot RAM to begin
programming the external memory. System bus
changes to an inactive state.
Boot loader program performs the necessary
external TBLWT and TBLWRD instructions to
perform programming functions.
When the boot loader program is finished pro-
gramming external memory, jump to known valid
external program memory location and clear
PGRM bit in MEMCON register to set Boot RAM
as data memory, or reset the part.
4.2
Return Address Stack
The return address stack allows any combination of up to
31 program calls and interrupts to occur. The PC (Pro-
gram Counter) is pushed onto the stack when a PUSH,
CALL
or RCALL instruction is executed, or an interrupt is
acknowledged. The PC value is pulled off the stack on a
RETURN, RETLW
or a RETFIE instruction. PCLATU and
PCLATH are not affected by any of the return instructions.
The stack operates as a 31-word by 21-bit stack memory
and a five-bit stack pointer, with the stack pointer initial-
ized to 00000b after all RESETS. There is no RAM asso-
ciated with stack pointer 00000b. This is only a RESET
value. During a CALL type instruction, causing a push
onto the stack, the stack pointer is first incremented and
the RAM location pointed to by the stack pointer is written
with the contents of the PC. During a RETURN type
instruction, causing a pop from the stack, the contents of
the RAM location indicated by the STKPTR is transferred
to the PC and then the stack pointer is decremented.
The stack space is not part of either program or data
space. The stack pointer is readable and writable, and
the data on the top of the stack is readable and writable
through SFR registers. Status bits STKOVF and
STKUNF in STKPTR register, indicate whether stack
over/underflow has occurred or not.
4.2.1
TOP-OF-STACK ACCESS
The top of the stack is readable and writable. Three
register locations, TOSU, TOSH and TOSL, allow
access to the contents of the stack location indicated by
the STKPTR register. This allows users to implement a
software stack, if necessary. After a CALL, RCALL or
interrupt, the software can read the pushed value by
reading the TOSU, TOSH and TOSL registers. These
values can be placed on a user defined software stack.
At return time, the software can replace the TOSU,
TOSH and TOSL and do a return.
The user should disable the global interrupt enable bits
during this time to prevent inadvertent stack operations.
4.2.2
RETURN STACK POINTER
(STKPTR)
The STKPTR register contains the stack pointer value,
the STKFUL (stack full) status bit, and the STKUNF
(stack underflow) status bits. Register 4-1 shows the
STKPTR register. The value of the stack pointer can be
0 through 31. The stack pointer increments when val-
ues are pushed onto the stack and decrements when
values are popped off the stack. At RESET, the stack
pointer value will be 0. The user may read and write the
stack pointer value. This feature can be used by a Real
Time Operating System for return stack maintenance.
After the PC is pushed onto the stack 31 times (without
popping any values off the stack), the STKFUL bit is
set. The STKFUL bit can only be cleared in software or
by a POR. Any subsequent push operation that causes
stack overflow will be ignored.
The action that takes place when the stack becomes
full, depends on the state of STVREN (stack overflow
RESET enable) configuration bit in CONFIG4L regis-
ter. Refer to Section 4.2.4 for more information. If
STVREN is set (default), stack over/underflow will set
the STKFUL bit, and reset the device. The STKFUL bit
will remain set and the stack pointer will be set to 0.
If STVREN is cleared, the STKFUL bit will be set on the
31st push and the stack pointer will increment to 31. All
subsequent push attempts will be ignored and
STKPTR remains at 31.
When the stack has been popped enough times to
unload the stack, the next pop will return a value of zero
to the PC and sets the STKUNF bit, while the stack
pointer remains at 0. The STKUNF bit will remain set
until cleared in software, or a POR occurs.
Note:
Returning a value of zero to the PC on an
underflow has the effect of vectoring the
program to the RESET vector, where the
stack conditions can be verified and appro-
priate actions can be taken.
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