MOVSS [z
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� PIC18F1330-I/ML
寤犲晢锛� Microchip Technology
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鏂囦欢澶�?銆�?/td> 0K
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8-bit PIC® Microcontroller Portfolio
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鏍稿績铏曠悊鍣細 PIC
鑺珨灏哄锛� 8-浣�
閫熷害锛� 40MHz
閫i€氭€э細 UART/USART
澶栧湇瑷�(sh猫)鍌欙細 娆犲妾㈡脯/寰�(f霉)浣�锛孡VD锛孭OR锛孭WM锛學DT
杓稿叆/杓稿嚭鏁�(sh霉)锛� 16
绋嬪簭瀛樺劜鍣ㄥ閲忥細 8KB锛�4K x 16锛�
绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 闁冨瓨
EEPROM 澶�?銆�?/td> 128 x 8
RAM 瀹归噺锛� 256 x 8
闆诲 - 闆绘簮 (Vcc/Vdd)锛� 4.2 V ~ 5.5 V
鏁�(sh霉)鎿�(j霉)杞�(zhu菐n)鎻涘櫒锛� A/D 4x10b
鎸暕鍣ㄥ瀷锛� 鍏�(n猫i)閮�
宸ヤ綔婧害锛� -40°C ~ 85°C
灏佽/澶栨锛� 28-VQFN 瑁搁湶鐒婄洡
鍖呰锛� 绠′欢
鐢�(ch菐n)鍝佺洰閷勯爜闈細 642 (CN2011-ZH PDF)
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PIC18F1230/1330
DS39758D-page 260
2009 Microchip Technology Inc.
MOVSS
Move Indexed to Indexed
Syntax:
MOVSS [zs], [zd]
Operands:
0
zs 127
0
zd 127
Operation:
((FSR2) + zs) ((FSR2) + zd)
Status Affected:
None
Encoding:
1st word (source)
2nd word (dest.)
1110
1111
1011
xxxx
1zzz
xzzz
zzzzs
zzzzd
Description
The contents of the source register are
moved to the destination register. The
addresses of the source and destination
registers are determined by adding the
7-bit literal offsets 鈥榸s鈥� or 鈥榸d鈥�,
respectively, to the value of FSR2. Both
registers can be located anywhere in
the 4096-byte data memory space
(000h to FFFh).
The MOVSS instruction cannot use the
PCL, TOSU, TOSH or TOSL as the
destination register.
If the resultant source address points to
an indirect addressing register, the
value returned will be 00h. If the
resultant destination address points to
an indirect addressing register, the
instruction will execute as a NOP.
Words:
2
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Determine
source addr
Determine
source addr
Read
source reg
Decode
Determine
dest addr
Determine
dest addr
Write
to dest reg
Example:
MOVSS [05h], [06h]
Before Instruction
FSR2
=
80h
Contents
of 85h
=
33h
Contents
of 86h
=
11h
After Instruction
FSR2
=
80h
Contents
of 85h
=
33h
Contents
of 86h
=
33h
PUSHL
Store Literal at FSR2, Decrement FSR2
Syntax:
PUSHL k
Operands:
0
k 255
Operation:
k
(FSR2),
FSR2 鈥� 1
FSR2
Status Affected: None
Encoding:
1110
1010
kkkk
Description:
The 8-bit literal 鈥榢鈥� is written to the data
memory address specified by FSR2. FSR2
is decremented by 1 after the operation.
This instruction allows users to push values
onto a software stack.
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read 鈥榢鈥�
Process
data
Write to
destination
Example:
PUSHL 08h
Before Instruction
FSR2H:FSR2L
=
01ECh
Memory (01ECh)
=
00h
After Instruction
FSR2H:FSR2L
=
01EBh
Memory (01ECh)
=
08h
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