• 參數(shù)資料
    型號(hào): PIC18F2331-I/MM
    廠商: Microchip Technology
    文件頁數(shù): 104/119頁
    文件大?。?/td> 0K
    描述: IC PIC MCU FLASH 4KX16 28QFN
    產(chǎn)品培訓(xùn)模塊: PIC18 J Series MCU Overview
    標(biāo)準(zhǔn)包裝: 61
    系列: PIC® 18F
    核心處理器: PIC
    芯體尺寸: 8-位
    速度: 40MHz
    連通性: I²C,SPI,UART/USART
    外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
    輸入/輸出數(shù): 24
    程序存儲(chǔ)器容量: 8KB(4K x 16)
    程序存儲(chǔ)器類型: 閃存
    EEPROM 大?。?/td> 256 x 8
    RAM 容量: 768 x 8
    電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
    數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
    振蕩器型: 內(nèi)部
    工作溫度: -40°C ~ 85°C
    封裝/外殼: 28-VQFN 裸露焊盤
    包裝: 管件
    產(chǎn)品目錄頁面: 642 (CN2011-ZH PDF)
    配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
    I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
    其它名稱: PIC18F2331-I/ML
    PIC18F2331-I/ML-ND
    Micrel, Inc.
    KSZ8842-PMQL/PMBL
    October 2007
    85
    M9999-100207-1.5
    Bit
    Default
    R/W
    Description
    “Diffserv” or “802.1p” classification is not enabled or fails to classify.
    10 = ingress packets on port 1 will be classified as priority 2 queue if
    “Diffserv” or “802.1p” classification is not enabled or fails to classify.
    11 = ingress packets on port 1 will be classified as priority 3 queue if
    “Diffserv” or “802.1p” classification is not enabled or fails to classify.
    Note: “Diffserv”, “802.1p” and port priority can be enabled at the same
    time. The OR’ed result of 802.1p and DSCP overwrites the port priority.
    2
    0
    RW
    Tag insertion
    1 = when packets are output on the port, the switch will add 802.1p/q tags
    to packets without 802.1p/q tags when received. The switch will not add
    tags to packets already tagged. The tag inserted is the ingress port’s “port
    VID”.
    0 = disable tag insertion
    1
    0
    RW
    Tag removal
    1 = when packets are output on the port, the switch will remove 802.1p/q
    tags from packets with 802.1p/q tags when received. The switch will not
    modify packets received without tags.
    0 = disable tag removal
    0
    RW
    TX Multiple Queues Select Enable
    1 = the port output queue is split into four priority queues.
    0 = single output queue on the port. There is no priority differentiation
    even though packets are classified into high or low priority.
    Port 2 Control Register 2 (Offset 0x0522): P2CR2
    This register contains the global per port control for the switch port 2 function.
    Bit
    Default
    R/W
    Description
    15
    reserved
    Reserved
    14
    0
    RW
    Ingress VLAN filtering
    1 = the switch will discard packets whose VID port membership in VLAN
    table bits [18:16] does not include the ingress port.
    0 = no ingress VLAN filtering.
    13
    0
    RW
    Discard Non PVID packets
    1 = the switch will discard packets whose VID does not match ingress port
    default VID.
    0 = no packets will be discarded.
    12
    0
    RW
    Force flow control
    1 = will always enable flow control on the port, regardless of AN result.
    0 = the flow control is enabled based on AN result.
    11
    0
    RW
    Back pressure enable
    1 = enable port’s half duplex back pressure
    0 = disable port’s half duplex back pressure.
    10
    1
    RW
    Transmit enable
    1 = enable packet transmission on the port
    0 = disable packet transmission on the port
    9
    1
    RW
    Receive enable
    1 = enable packet reception on the port
    0 = disable packet reception on the port
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