參數(shù)資料
型號: PIC18F2331T-E/SOG
廠商: Microchip Technology
文件頁數(shù): 21/119頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 28SOIC
標準包裝: 1,600
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 帶卷 (TR)
配用: I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
其它名稱: PIC18F2331T-E/SOGR
PIC18F2331T-E/SOGR-ND
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
117
M9999-100207-1.5
Acronyms and Glossary
BPDU Bridge Protocol Data Unit
A packet containing ports, addresses, etc. to make sure data being
passed through a bridged network arrives at its proper destination.
CMOSComplementary Metal Oxide Semiconductor. A common semiconductor manufacturing technique in which positive and
negative types of transistors are combined to form a current gate that
in turn forms an effective means of controlling electrical current
through a chip.
CRC Cyclic Redundancy Check
A common technique for detecting
data transmission errors. CRC
for Ethernet is 32 bits long.
DA
Destination Address
The address to send packets.
DMA Direct Memory Access
A design in which memory on a chip is controlled independently of
the CPU.
EISA Extended Industry Standard Architecture
A
bus architecture designed for PCs using 80x86 processors, or an
Intel 80386, 80486 or Pentium microprocessor. EISA buses are 32
bits wide and support multiprocessing.
EMI
Electro-Magnetic Interference
A naturally occurring phenomena when the electromagnetic field of
one device disrupts, impedes or degrades the electromagnetic field of
another device by coming into proximity with it. In computer
technology, computer devices are susceptible to EMI because
electromagnetic fields are a byproduct of passing electricity through a
wire. Data lines that have not been properly shielded are susceptible
to data corruption by EMI.
FCS
Frame Check Sequence
See CRC.
FID
Frame or Filter ID
Specifies the frame identifier. Alternately is the filter identifier.
IPG
Inter-Packet Gap
A time delay between successive data packets mandated by the
network standard for protocol reasons. In Ethernet, the medium has
to be "silent" (i.e., no data transfer) for a short period of time before a
node can consider the network idle and start to transmit. IPG is used
to correct timing differences between a transmitter and receiver.
During the IPG, no data is transferred, and information in the gap can
be discarded or additions inserted without impact on data integrity.
ISI
Inter-Symbol Interference
T
he disruption of transmitted code caused by adjacent pulses
affecting or interfering with each other.
ISA
Industry Standard Architecture
A bus architecture used in the IBM PC/XT and
PC/AT.
MDI
Medium Dependent Interface
An Ethernet port connection that allows network hubs or switches to
connect to other hubs or switches without a null-modem, or
crossover, cable. MDI provides the standard interface to a particular
media (copper or fiber) and is therefore 'media dependent.'
MDI-X Medium Dependent Interface Crossover
An Ethernet port connection that allows networked end stations (i.e.,
PCs or workstations) to connect to each other using a null-modem, or
crossover, cable. For 10/100 full-duplex networks, an end point (such
as a computer) and a switch are wired so that each transmitter
connects to the far end receiver. When connecting two computers
together, a cable that crosses the TX and RX is required to do this.
With auto MDI-X, the PHY senses the correct TX and RX roles,
eliminating any cable confusion.
MIB
Management Information Base
The MIB comprises the management portion of network devices. This
can include things like monitoring traffic levels and faults (statistical),
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