參數(shù)資料
型號: PIC18F242-I/SP
廠商: Microchip Technology
文件頁數(shù): 121/134頁
文件大小: 0K
描述: IC MCU FLASH 8KX16 EE A/D 28DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 23
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 5x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
配用: DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
其它名稱: PIC18F242I/SP
1997 Microchip Technology Inc.
DS30444E - page 87
PIC16C9XX
12.8
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP1 module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be pro-
grammed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the ADRES to
the desired location). The appropriate analog input
channel must be selected and the minimum acquisition
done before the “special event trigger” sets the
GO/DONE bit (starts a conversion).
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
12.9
Connection Considerations
If the input voltage exceeds the rail values (VSS or VDD)
by greater than 0.2V, then the accuracy of the conver-
sion is out of specication.
An external RC lter is sometimes added for anti-alias-
ing of the input signal. The R component should be
selected to ensure that the total source impedance is
kept under the 10 k
recommended specication. Any
external components connected (via hi-impedance) to
an analog input pin (capacitor, zener diode, etc.) should
have very little leakage current at the pin.
12.10
Transfer Function
The ideal transfer function of the A/D converter is as fol-
lows: the rst transition occurs when the analog input
voltage (VAIN) is Analog VREF / 256 (Figure 12-5).
FIGURE 12-5: A/D TRANSFER FUNCTION
Digital
code
output
FFh
FEh
04h
03h
02h
01h
00h
0.5
LSb
1
LSb
2
LSb
3
LSb
4
LSb
255
LSb
256
LSb
(full
scale)
Analog input voltage
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