參數(shù)資料
型號(hào): PIC18F2423-I/SP
廠商: Microchip Technology
文件頁數(shù): 24/54頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 28-DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產(chǎn)品目錄頁面: 642 (CN2011-ZH PDF)
配用: DVA18XP280-ND - DEVICE ADAPTER 18F2220 PDIP 28LD
PIC18F2423/2523/4423/4523
DS39755C-page 30
2009 Microchip Technology Inc.
2.1
A/D Acquisition Requirements
For the A/D Converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 2-3.
The source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor, CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD). The source impedance affects the offset voltage
at the analog input (due to pin leakage current). The
maximum recommended impedance for analog
sources is 2.5 k
Ω.
After the analog input channel is selected (changed),
the channel must be sampled for at least the minimum
acquisition time before starting a conversion.
To calculate the minimum acquisition time, Equation 2-1
may be used. This equation assumes that 1/2 LSb error
is used (4,096 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
Example 2-3 shows the calculation of the minimum
required acquisition time, TACQ. This calculation is
based on the application system assumptions shown in
EQUATION 2-1:
ACQUISITION TIME
EQUATION 2-2:
A/D MINIMUM CHARGING TIME
EQUATION 2-3:
CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME
Note:
When the conversion is started, the
holding capacitor is disconnected from the
input pin.
TABLE 2-1:
TACQ ASSUMPTIONS
CHOLD
=
25 pF
Rs
=
2.5 k
Ω
Conversion Error
1/2 LSb
VDD
=3V
→ Rss = 4 kΩ
Temperature
=
85
°C (system maximum)
TACQ
=
Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient
=TAMP + TC + TCOFF
VHOLD
=
(VREF – (VREF/4096)) (1 – e(-TC/CHOLD(RIC + RSS + RS)))
or
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4096)
TACQ
=TAMP + TC + TCOFF
TAMP
=0.2
μs
TCOFF
=
(Temp – 25
°C)(0.02 μs/°C)
(85
°C – 25°C)(0.02 μs/°C)
1.2
μs
Temperature coefficient is only required for temperatures > 25
°C. Below 25°C, TCOFF = 0 ms.
TC
=
-(CHOLD)(RIC + RSS + RS) ln(1/4095)
μs
-(25 pF) (1 k
Ω + 4 kΩ + 2.5 kΩ) ln(0.0004883) μs
1.56
μs
TACQ
=0.2
μs + 1.56 μs + 1.2 μs
2.96
μs
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