參數(shù)資料
型號: PIC18F25J10-I/SS
廠商: Microchip Technology
文件頁數(shù): 14/80頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 16KX16 28SSOP
產品培訓模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 47
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據轉換器: A/D 10x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
產品目錄頁面: 643 (CN2011-ZH PDF)
配用: AC162074-ND - HEADER INTRFC MPLAB ICD2 44TQFP
MA180011-ND - MODULE PLUG-IN 18F25J10 28SOIC
AC162067-ND - HEADER INTRFC MPLAB ICD2 40/28P
AC164331-ND - MODULE SKT FOR 28SSOP 18F45J10
PIC16F8X
1998 Microchip Technology Inc.
DS30430C-page 21
5.0
I/O PORTS
The PIC16F8X has two ports, PORTA and PORTB.
Some port pins are multiplexed with an alternate func-
tion for other features on the device.
5.1
PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger
input and an open drain output. All other RA port pins
have TTL input levels and full CMOS output drivers. All
pins have data direction bits (TRIS registers) which can
configure these pins as output or input.
Setting a TRISA bit (=1) will make the corresponding
PORTA pin an input, i.e., put the corresponding output
driver in a hi-impedance mode. Clearing a TRISA bit
(=0) will make the corresponding PORTA pin an output,
i.e., put the contents of the output latch on the selected
pin.
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The RA4 pin is multiplexed with the TMR0 clock input.
FIGURE 5-1:
BLOCK DIAGRAM OF PINS
RA3:RA0
EXAMPLE 5-1:
INITIALIZING PORTA
CLRF
PORTA
; Initialize PORTA by
; setting output
; data latches
BSF
STATUS, RP0
; Select Bank 1
MOVLW
0x0F
; Value used to
; initialize data
; direction
MOVWF
TRISA
; Set RA<3:0> as inputs
; RA4 as outputs
; TRISA<7:5> are always
; read as ’0’.
FIGURE 5-2:
BLOCK DIAGRAM OF PIN RA4
Note: I/O pins have protection diodes to VDD and VSS.
Data
bus
Q
D
Q
CK
Q
D
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
TTL
input
buffer
VSS
VDD
I/O pin
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
VSS
RA4 pin
TMR0 clock input
Note: I/O pin has protection diodes to VSS only.
Q
D
Q
CK
Q
D
Q
CK
EN
QD
EN
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