參數(shù)資料
型號: PIC18F25K20-I/SO
廠商: Microchip Technology
文件頁數(shù): 20/42頁
文件大小: 0K
描述: IC PIC MCU FLASH 16KX16 28SOIC
產(chǎn)品培訓(xùn)模塊: PIC18 K-Series
XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 27
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 24
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 11x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SOIC(0.295",7.50mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 656 (CN2011-ZH PDF)
配用: AC164112-ND - VOLTAGE LIMITER MPLAB ICD2 VPP
2009 Microchip Technology Inc.
Advance Information
DS41297F-page 27
PIC18F2XK20/4XK20
FIGURE 4-4:
SHIFT OUT DATA HOLDING REGISTER TIMING DIAGRAM (0010)
FIGURE 4-5:
HIGH-IMPEDANCE DELAY
4.5
Verify Data EEPROM
A data EEPROM address may be read via a sequence
of core instructions (4-bit command, ‘0000’) and then
output on PGD via the 4-bit command, ‘0010’ (TABLAT
register).
The
result
may
then
be
immediately
compared to the appropriate data in the programmer’s
memory for verification. Refer to Section 4.4 “Read
Data EEPROM Memory” for implementation details of
reading data EEPROM.
4.6
Blank Check
The term “Blank Check” means to verify that the device
has no programmed memory cells. All memories must
be verified: code memory, data EEPROM, ID locations
and Configuration bits. The device ID registers
(3FFFFEh:3FFFFFh) should be ignored.
A “blank” or “erased” memory cell will read as a ‘1’.
Therefore, Blank Checking a device merely means to
verify that all bytes read as FFh except the Configura-
tion bits. Unused (reserved) Configuration bits will read
‘0’ (programmed). Refer to Table 5-1 for blank configu-
ration expect data for the various PIC18F2XK20/
4XK20 devices.
Given that Blank Checking is merely code and data
EEPROM verification with FFh expect data, refer to
for implementation details.
FIGURE 4-6:
BLANK CHECK FLOW
12
3
4
PGC
P5
PGD
PGD = Input
Shift Data Out
P6
PGD = Output
56
7
8
1
23
4
P5A
910
11
13
15
16
14
12
Fetch Next 4-bit Command
01
0
PGD = Input
LSb
MSb
12
34
56
12
3
4
nn
n
P14
(Note 1)
Note
1:
Magnification of the High-Impedance delay between PGC and PGD is shown in Figure 4-5.
(Note 1)
MSb
nn
1
2
P19
PGD
PGC
P3
Yes
No
Start
Blank Check Device
Is
device
blank?
Continue
Abort
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