2009 Microchip Technology Inc.
DS39636D-page 175
PIC18F2X1X/4X1X
FIGURE 16-14:
I2C SLAVE MODE TIMING SEN = 1 (RECEPTION, 10-BIT ADDRESS)
SD
A
SC
L
S
SPI
F
B
F
(
S
PST
A
T
<0
>)
S
1
2
3
4
56
7
8
9
1
23
4
5
6
7
8
9
1
2
3
4
5
7
8
9
P
1
0
A
9
A
8
A
7
A
6
A
5
A
4A
3A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
1
D
0
Re
ce
ive
Da
ta
B
yte
AC
K
R/W
=
0
ACK
Receive
F
irst
B
yte
o
fA
ddre
ss
C
lea
re
di
n
s
o
ftw
a
re
D2
6
(P
IR
1<
3>
)
Cl
ea
re
din
so
ftwa
re
R
e
cei
ve
S
e
co
nd
B
yte
of
A
d
dr
ess
C
le
ar
ed
by
har
dw
are
w
h
en
S
P
A
D
is
upda
ted
w
ith
lo
w
by
te
of
addr
ess
af
ter
falling
ed
ge
UA
(
S
SPS
TA
T
<
1
>
)
Clo
ck
is
h
e
ld
lo
w
u
ntil
up
date
o
fS
S
P
A
D
ha
s
ta
ken
pl
ace
U
A
is
set
in
di
cati
ng
that
th
e
S
P
A
D
n
eeds
to
be
update
d
UA
is
se
tindicatin
g
that
S
P
A
DD
nee
ds
to
b
e
upda
ted
Cle
a
re
d
b
yh
a
rd
wa
re
wh
en
S
P
A
D
is
u
pdate
d
w
ith
hi
gh
byte
of
ad
dress
a
fte
rfa
lli
ng
edge
SSP
BUF
is
wr
itt
e
n
w
ith
co
ntent
so
fS
S
P
S
R
D
u
mm
yread
of
S
P
B
U
F
to
clear
B
F
flag
AC
K
CK
P
12
3
4
5
7
8
9
D
7
D6
D5
D4
D3
D1
D0
Re
ce
ive
Da
ta
Byte
B
u
sm
a
ster
te
rmi
na
tes
tr
ansfe
r
D2
6
AC
K
Cle
ar
e
d
in
so
ftwa
re
C
lea
re
di
n
s
o
ftw
a
re
SS
PO
V
(
SSP
CO
N1
<6
>)
CK
P
written
to
‘1
’
No
te
:
An
u
p
d
a
te
o
ft
he
SSP
AD
D
re
g
is
te
rb
e
fo
re
th
efa
llin
g
e
d
g
eo
fth
e
n
in
th
cl
ock
w
ill
h
a
ve
n
oe
ffe
ct
o
n
UA
a
n
d
UA
will
r
e
m
a
in
se
t.
No
te
:
A
n
updat
e
of
the
S
P
A
D
re
g
is
ter
be
fo
re
t
h
ef
al
lin
g
ed
g
e
o
fth
en
in
th
clo
ck
will
ha
ve
n
o
ef
fect
on
U
A
and
UA
will
r
em
a
in
se
t.
in
so
ftwa
re
Clo
ck
is
h
e
ld
lo
w
u
n
til
upda
te
of
S
P
A
D
has
ta
ke
n
pl
ac
e
of
n
inth
cl
ock
of
ni
nth
cl
ock
SS
PO
V
is
s
e
t
be
cause
S
P
B
U
F
is
still
fu
ll.
ACK
is
not
se
nt.
D
u
m
yr
ead
of
S
P
B
U
F
to
cl
ea
rB
F
flag
Clo
ck
is
h
eld
lo
w
u
n
til
CK
P
is
se
tto
‘1
’
Clo
ck
is
n
o
th
e
ld
lo
w
be
ca
u
se
A
C
K
=
1