參數(shù)資料
型號: PIC18F4331-I/P
廠商: Microchip Technology
文件頁數(shù): 7/119頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 4KX16 40DIP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 10
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲器容量: 8KB(4K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁面: 645 (CN2011-ZH PDF)
配用: I3-DB18F4431-ND - BOARD DAUGHTER ICEPIC3
DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
Micrel, Inc.
KSZ8842-PMQL/PMBL
October 2007
104
M9999-100207-1.5
Offset
Counter Name
Description
length
0x11
Rx256to511Octets
Total Rx packets (bad packets included) that are between 256 and 511 octets in
length
0x12
Rx512to1023Octets
Total Rx packets (bad packets included) that are between 512 and 1023 octets in
length
0x13
Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 1024 and 1522 octets in
length (upper limit depends on max packet size setting)
0x14
TxLoPriorityByte
Tx lo-priority good octet count, including PAUSE packets
0x15
TxHiPriorityByte
Tx hi-priority good octet count, including PAUSE packets
0x16
TxLateCollision
The number of times a collision is detected later than 512 bit-times into the Tx of a
packet
0x17
TxPausePkts
Number of PAUSE frames transmitted by a port
0x18
TxBroadcastPkts
Tx good broadcast packets (not including error broadcast or valid multicast packets)
0x19
TxMulticastPkts
Tx good multicast packets (not including error multicast packets or valid broadcast
packets)
0x1A
TxUnicastPkts
Tx good unicast packets
0x1B
TxDeferred
Tx packets by a port for which the 1st Tx attempt is delayed due to the busy medium
0x1C
TxTotalCollision
Tx total collision, half duplex only
0x1D
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
0x1E
TxSingleCollision
Successfully Tx frames on a port for which Tx is inhibited by exactly one collision
0x1F
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than one
collision
Table 9. Port 1s “Per Port” MIB Counters Indirect Memory Offsets
Format of “All Port Dropped Packet” MIB Counters
Bit
Default
R/W
Description
30 – 16
N/A
Reserved
15 – 0
RO
Counter Value
Table 10. “All Port Dropped Packet” MIB Counters Format
Note: “All Port Dropped Packet” MIB Counters do not indicate overflow or validity; therefore, the application must keep track of overflow and
valid
conditions.
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 11.
Offset
Counter Name
Description
0x100
Port1 TX Drop Packets
TX packets dropped due to lack of resources
0x101
Port2 TX Drop Packets
TX packets dropped due to lack of resources
0x103
Port1 RX Drop Packets
RX packets dropped due to lack of resources
0x104
Port2 RX Drop Packets
RX packets dropped due to lack of resources
Table 11. “All Port Dropped Packet” MIB Counters Indirect Memory Offsets
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