參數(shù)資料
型號(hào): PIC18F4431-I/P
廠商: Microchip Technology
文件頁(yè)數(shù): 39/119頁(yè)
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 40DIP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 10
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,電源控制 PWM,QEI,POR,PWM,WDT
輸入/輸出數(shù): 36
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類(lèi)型: 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 9x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 40-DIP(0.600",15.24mm)
包裝: 管件
產(chǎn)品目錄頁(yè)面: 645 (CN2011-ZH PDF)
配用: DVA18XP400-ND - DEVICE ADAPTER 18F4220 PDIP 40LD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
ACICE0206-ND - ADAPTER MPLABICE 40P 600 MIL
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PIC18F2331/2431/4331/4431
DS39616D-page 26
2010 Microchip Technology Inc.
2.2
Power Supply Pins
2.2.1
DECOUPLING CAPACITORS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS, is required.
Consider the following criteria when using decoupling
capacitors:
Value and type of capacitor: A 0.1
F (100 nF),
10-20V capacitor is recommended. The capacitor
should be a low-ESR device, with a resonance
frequency in the range of 200 MHz and higher.
Ceramic capacitors are recommended.
Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is no greater
than 0.25 inch (6 mm).
Handling high-frequency noise: If the board is
experiencing high-frequency noise (upward of
tens of MHz), add a second ceramic type capaci-
tor in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01
F to 0.001 F. Place this
second capacitor next to each primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible
(e.g., 0.1
F in parallel with 0.001 F).
Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB trace
inductance.
2.2.2
TANK CAPACITORS
On boards with power traces running longer than
six inches in length, it is suggested to use a tank capac-
itor for integrated circuits, including microcontrollers, to
supply a local power source. The value of the tank
capacitor should be determined based on the trace
resistance that connects the power supply source to
the device, and the maximum current drawn by the
device in the application. In other words, select the tank
capacitor so that it meets the acceptable voltage sag at
the device. Typical values range from 4.7
F to 47 F.
2.2.3
CONSIDERATIONS WHEN USING
BOR
When the Brown-out Reset (BOR) feature is enabled,
a sudden change in VDD may result in a spontaneous
BOR event. This can happen when the microcontroller
is operating under normal operating conditions, regard-
less of what the BOR set point has been programmed
to, and even if VDD does not approach the set point.
The precipitating factor in these BOR events is a rise or
fall in VDD with a slew rate faster than 0.15V/
s.
An application that incorporates adequate decoupling
between the power supplies will not experience such
rapid voltage changes. Additionally, the use of an
electrolytic tank capacitor across VDD and VSS, as
described above, will be helpful in preventing high slew
rate transitions.
If the application has components that turn on or off,
and share the same VDD circuit as the microcontroller,
the BOR can be disabled in software by using the
SBOREN bit before switching the component. After-
wards, allow a small delay before re-enabling the BOR.
By doing this, it is ensured that the BOR is disabled
during the interval that might cause high slew rate
changes of VDD.
Note:
Not all devices incorporate software BOR
control. See Section 5.0 “Reset” for
device-specific information.
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