參數(shù)資料
型號： PIC18F4450-I/PT
廠商： Microchip Technology
文件頁數(shù)： 182/241頁
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 8KX16 44TQFP
產(chǎn)品培訓模塊： Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝： 160
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 48MHz
連通性： UART/USART，USB
外圍設備： 欠壓檢測/復位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 34
程序存儲器容量： 16KB（8K x 16）
程序存儲器類型： 閃存
RAM 容量： 768 x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 13x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-TQFP
包裝： 托盤
產(chǎn)品目錄頁面： 646 (CN2011-ZH PDF)
配用： DM163025-ND - PIC DEM FULL SPEED USB DEMO BRD
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
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2010 Microchip Technology Inc.
DS70141F-page 45
dsPIC30F3010/3011
5.0
INTERRUPTS
The dsPIC30F3010/3011 has 29 interrupt sources and
4 processor exceptions (traps), which must be
arbitrated based on a priority scheme.
The CPU is responsible for reading the Interrupt
Vector Table (IVT) and transferring the address con-
tained in the interrupt vector to the program counter.
The interrupt vector is transferred from the program
data bus into the program counter through a 24-bit
wide multiplexer on the input of the program counter.
The Interrupt Vector Table (IVT) and Alternate
Interrupt Vector Table (AIVT) are placed near the
beginning of program memory (0x000004). The IVT
and AIVT are shown in Figure 5-1.
The
interrupt
controller
is
responsible
for
pre-
processing the interrupts and processor exceptions,
prior to their being presented to the processor core.
The peripheral interrupts and traps are enabled,
prioritized and controlled using centralized Special
Function Registers (SFR):
IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their respec-
tive peripherals or external signals, and they are
cleared via software.
IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
IPC0<15:0>... IPC11<7:0>
The user-assignable priority level associated with
each of these interrupts is held centrally in these
twelve registers.
IPL<3:0> The current CPU priority level is
explicitly stored in the IPL bits. IPL<3> is present
in the CORCON register, whereas IPL<2:0> are
present in the STATUS Register (SR) in the
processor core.
INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the
control and status flags for the processor
exceptions. The INTCON2 register controls the
external interrupt request signal behavior and the
use of the alternate vector table.
All interrupt sources can be user-assigned to one of
7 priority levels, 1 through 7, through the IPCx regis-
ters. Each interrupt source is associated with an inter-
rupt vector, as shown in Table 5-1. Levels 7 and 1
represent the highest and lowest maskable priorities,
respectively.
If the NSTDIS bit (INTCON1<15>) is set, nesting of
interrupts is prevented. Thus, if an interrupt is currently
being serviced, processing of a new interrupt is
prevented, even if the new interrupt is of higher priority
than the one currently being serviced.
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts, inter-
rupt-on-change, etc. Control of these features remains
within the peripheral module which generates the
interrupt.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instructions, during which the DISI bit
(INTCON2<14>) remains set.
When an interrupt is serviced, the PC is loaded with the
address stored in the vector location in program
memory that corresponds to the interrupt. There are 63
different vectors within the IVT (refer to Figure 5-2).
These vectors are contained in locations 0x000004
through 0x0000FE of program memory (refer to
Figure 5-2). These locations contain 24-bit addresses,
and in order to preserve robustness, an address error
trap will take place should the PC attempt to fetch any
of these words during normal execution. This prevents
execution of random data as a result of accidentally
decrementing a PC into vector space, accidentally
mapping a data space address into vector space or the
PC rolling over to 0x000000 after reaching the end of
implemented program memory space. Execution of a
GOTO
instruction to this vector space will also generate
an address error trap.
Note:
This data sheet summarizes features of
this group of dsPIC30F devices and is not
intended to be a complete reference
source. For more information on the CPU,
peripherals,
register
descriptions
and
general device functionality, refer to the
“dsPIC30F Family Reference Manual”
(DS70046). For more information on the
device instruction set and programming,
refer to the “16-bit MCU and DSC
Programmer’s
Reference
Manual”
(DS70157).
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its
corresponding
enable
bit.
User
software should ensure the appropriate
Interrupt flag bits are clear prior to
enabling an interrupt.
Note:
Assigning a priority level of 0 to an
interrupt source is equivalent to disabling
that interrupt.
Note:
The IPL bits become read-only whenever
the NSTDIS bit has been set to ‘1’.
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