參數(shù)資料
型號: PIC18F44J10T-I/ML
廠商: Microchip Technology
文件頁數(shù): 47/80頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 8KX16 44QFN
標(biāo)準(zhǔn)包裝: 1
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 剪切帶 (CT)
配用: AC162074-ND - HEADER INTRFC MPLAB ICD2 44TQFP
MA180013-ND - MODULE PLUG-IN 18F45J10 44TQFP
AC162067-ND - HEADER INTRFC MPLAB ICD2 40/28P
其它名稱: PIC18F44J10T-I/MLCT
PIC16F8X
1998 Microchip Technology Inc.
DS30430C-page 51
8.11
Watchdog Timer (WDT)
The Watchdog Timer is a free running on-chip RC
oscillator
which
does
not
require
any
external
components. This RC oscillator is separate from the
RC oscillator of the OSC1/CLKIN pin. That means that
the WDT will run even if the clock on the OSC1/CLKIN
and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP
instruction. During normal operation a WDT time-out
generates a device RESET. If the device is in SLEEP
mode, a WDT Wake-up causes the device to wake-up
and continue with normal operation. The WDT can be
permanently disabled by programming configuration bit
WDTE as a ’0’ (Section 8.1).
8.11.1
WDT PERIOD
The WDT has a nominal time-out period of 18 ms, (with
no
prescaler).
The
time-out
periods
vary
with
temperature, VDD and process variations from part to
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION_REG register. Thus, time-out
periods up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon
a WDT time-out.
8.11.2
WDT PROGRAMMING CONSIDERATIONS
It should also be taken into account that under worst
case conditions (VDD = Min., Temperature = Max., max.
WDT prescaler) it may take several seconds before a
WDT time-out occurs.
FIGURE 8-18: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 8-7
SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on all
other resets
2007h
Config. bits
(2)
PWRTE(1)
WDTE
FOSC1
FOSC0
(2)
81h
OPTION_
REG
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
Legend: x = unknown. Shaded cells are not used by the WDT.
Note 1:
See Figure 8-1 and Figure 8-2 for operation of the PWRTE bit.
2:
From TMR0 Clock Source
To TMR0 (Figure 6-6)
Postscaler
WDT Timer
M
U
X
PSA
8 - to -1 MUX
PSA
WDT
Time-out
1
0
1
WDT
Enable Bit
PS2:PS0
8
MUX
Note: PSA and PS2:PS0 are bits in the OPTION_REG register.
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