[ label ] CALL k Operands: 0 k " />
參數資料
型號: PIC18F4520-I/ML
廠商: Microchip Technology
文件頁數: 88/151頁
文件大?。?/td> 0K
描述: IC MCU FLASH 16KX16 44QFN
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 45
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數: 36
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數據轉換器: A/D 13x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產品目錄頁面: 643 (CN2011-ZH PDF)
配用: XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 355
PIC16(L)F1782/3
CALL
Call Subroutine
Syntax:
[ label ] CALL k
Operands:
0
k 2047
Operation:
(PC)+ 1
TOS,
k
PC<10:0>,
(PCLATH<6:3>)
PC<14:11>
Status Affected:
None
Description:
Call Subroutine. First, return address
(PC + 1) is pushed onto the stack.
The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper
bits of the PC are loaded from
PCLATH. CALL is a two-cycle instruc-
tion.
CALLW
Subroutine Call With W
Syntax:
[ label ] CALLW
Operands:
None
Operation:
(PC) +1
TOS,
(W)
PC<7:0>,
(PCLATH<6:0>)
PC<14:8>
Status Affected:
None
Description:
Subroutine call with W. First, the
return address (PC + 1) is pushed
onto the return stack. Then, the con-
tents of W is loaded into PC<7:0>,
and the contents of PCLATH into
PC<14:8>. CALLW is a two-cycle
instruction.
CLRF
Clear f
Syntax:
[ label ] CLRF
f
Operands:
0
f 127
Operation:
00h
(f)
1 Z
Status Affected:
Z
Description:
The contents of register ‘f’ are cleared
and the Z bit is set.
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h
(W)
1 Z
Status Affected:
Z
Description:
W register is cleared. Zero bit (Z) is
set.
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CLRWDT
Operands:
None
Operation:
00h
WDT
0 WDT prescaler,
1 TO
1 PD
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watch-
dog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
COMF
Complement f
Syntax:
[ label ] COMF
f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f)
(destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are com-
plemented. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’.
DECF
Decrement f
Syntax:
[ label ] DECF f,d
Operands:
0
f 127
d
[0,1]
Operation:
(f) - 1
(destination)
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ is ‘0’, the
result is stored in the W
register. If ‘d’ is ‘1’, the result is stored
back in register ‘f’.
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