參數(shù)資料
型號(hào)： PIC18F4580T-I/ML
廠商： Microchip Technology
文件頁(yè)數(shù)： 31/88頁(yè)
文件大小： 0K
描述： IC PIC MCU FLASH 16KX16 44QFN
標(biāo)準(zhǔn)包裝： 1,600
系列： PIC® 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 40MHz
連通性： CAN，I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，HLVD，POR，PWM，WDT
輸入/輸出數(shù)： 36
程序存儲(chǔ)器容量： 32KB（16K x 16）
程序存儲(chǔ)器類型： 閃存
EEPROM 大?。?/td> 256 x 8
RAM 容量： 1.5K x 8
電壓 - 電源 (Vcc/Vdd)： 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 11x10b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 44-VQFN 裸露焊盤(pán)
包裝： 帶卷 (TR)
2010 Microchip Technology Inc.
DS21801F-page 37
MCP2515
5.0
BIT TIMING
All nodes on a given CAN bus must have the same
nominal bit rate. The CAN protocol uses Non Return to
Zero (NRZ) coding, which does not encode a clock
within the data stream. Therefore, the receive clock
must be recovered by the receiving nodes and
synchronized to the transmitter’s clock.
As oscillators and transmission times may vary from
node to node, the receiver must have some type of
Phase
Lock
Loop
(PLL)
synchronized
to
data
transmission edges to synchronize and maintain the
receiver clock. Since the data is NRZ-coded, it is
necessary to include bit-stuffing to ensure that an edge
occurs at least every six bit times to maintain the Digital
Phase Lock Loop (DPLL) synchronization.
The bit timing of the MCP2515 is implemented using a
DPLL that is configured to synchronize to the incoming
data, as well as provide the nominal timing for the
transmitted data. The DPLL breaks each bit time into
multiple segments made up of minimal periods of time,
called the Time Quanta (TQ).
Bus timing functions executed within the bit time frame
(such as synchronization to the local oscillator, network
transmission delay compensation and sample point
positioning) are defined by the programmable bit timing
logic of the DPLL.
5.1
The CAN Bit TIme
All devices on the CAN bus must use the same bit rate.
However, all devices are not required to have the same
master oscillator clock frequency. For the different
clock frequencies of the individual devices, the bit rate
has to be adjusted by appropriately setting the baud
rate prescaler and number of time quanta in each
segment.
The CAN bit time is made up of non-overlapping
segments. Each of these segments are made up of
integer units called Time Quanta (TQ), explained later
in this data sheet. The Nominal Bit Rate (NBR) is
defined in the CAN specification as the number of bits
per second transmitted by an ideal transmitter with no
resynchronization. It can be described with the
equation:
EQUATION 5-1:
Nominal Bit Time
The Nominal Bit Time (NBT) (tbit) is made up of non-
overlapping segments (Figure 5-1). Therefore, the
NBT is the summation of the following segments:
Associated with the NBT are the sample point,
Synchronization Jump Width (SJW) and Information
Processing Time (IPT), which are explained later.
SYNCHRONIZATION SEGMENT
The Synchronization Segment (SyncSeg) is the first
segment in the NBT and is used to synchronize the
nodes on the bus. Bit edges are expected to occur
within the SyncSeg. This segment is fixed at 1 TQ.
FIGURE 5-1:
CAN BIT TIME SEGMENTS
NBR
f
bit
1
t
bit
-------
==
t
bit
t
SyncSeg
t
PropSeg
t
PS1
t
PS2
++
+
=
Nominal Bit Time (NBT), tbit
Sample
Point
SyncSeg
PropSeg
PhaseSeg1 (PS1)
PhaseSeg2 (PS2)
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