PIC18FXX8
DS41159B-page 80
Preliminary
2002 Microchip Technology Inc.
REGISTER 8-2:
INTCON2 REGISTER
R/W-1
RBPU
bit 7
R/W-1
INTEDG0
R/W-1
INTEDG1
U-0
—
U-0
—
R/W-1
TMR0IP
U-0
—
R/W-1
RBIP
bit 0
bit 7
RBPU
: PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
INTEDG0
: External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
INTEDG1
: External Interrupt 1 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
Unimplmented:
Read as
’
0
’
TMR0IP
: TMR0 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
Unimplmented:
Read as
’
0
’
RBIP
: RB Port Change Interrupt Priority bit
1
= High priority
0
= Low priority
bit 6
bit 5
bit 4-3
bit 2
bit 1
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’
1
’
= Bit is set
U = Unimplemented bit, read as
‘
0
’
’
0
’
= Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit, or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows software polling.
