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參數(shù)資料
| 型號： | PIC18F46J53-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 37/71頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU 64KB FLASH 44TQFP |
| 產(chǎn)品培訓模塊： | 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 160 |
| 系列： | PIC® XLP™ 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 48MHz |
| 連通性： | I²C，LIN，SPI，UART/USART，USB |
| 外圍設備： | 欠壓檢測/復位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 34 |
| 程序存儲器容量： | 64KB（32K x 16） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2.15 V ~ 3.6 V |
| 數(shù)據(jù)轉換器： | A/D 13x10b/12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 44-TQFP |
| 包裝： | 管件 |
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PIC18(L)F2X/4XK22
DS41412E-page 42
2010-2012 Microchip Technology Inc.
2.11.3
CLOCK SWITCH TIMING
When switching between one oscillator and another,
the new oscillator may not be operating which saves
power (see Figure 2-9). If this is the case, there is a
delay after the SCS<1:0> bits of the OSCCON register
are modified before the frequency change takes place.
The OSTS and IOFS bits of the OSCCON register will
reflect the current active status of the external and
HFINTOSC oscillators. The timing of a frequency
selection is as follows:
1.
SCS<1:0> bits of the OSCCON register are mod-
ified.
2.
The old clock continues to operate until the new
clock is ready.
3.
Clock switch circuitry waits for two consecutive
rising edges of the old clock after the new clock
ready signal goes true.
4.
The system clock is held low starting at the next
falling edge of the old clock.
5.
Clock switch circuitry waits for an additional two
rising edges of the new clock.
6.
On the next falling edge of the new clock the low
hold on the system clock is released and new
clock is switched in as the system clock.
7.
Clock switch is complete.
See Figure 2-1 for more details.
If the HFINTOSC is the source of both the old and new
frequency, there is no start-up delay before the new
frequency is active. This is because the old and new
frequencies are derived from the HFINTOSC via the
postscaler and multiplexer.
Start-up
delay
specifications
are
located
in
Specifications (Oscillator Module).
2.12
Two-Speed Clock Start-up Mode
Two-Speed Start-up mode provides additional power
savings by minimizing the latency between external
oscillator start-up and code execution. In applications
that make heavy use of the Sleep mode, Two-Speed
Start-up will remove the external oscillator start-up
time from the time spent awake and can reduce the
overall power consumption of the device.
This mode allows the application to wake-up from
Sleep, perform a few instructions using the HFINTOSC
as the clock source and go back to Sleep without
waiting for the primary oscillator to become stable.
When the oscillator module is configured for LP, XT or
HS modes, the Oscillator Start-up Timer (OST) is
enabled (see Section 2.5.1 “Oscillator Start-up Timer
(OST)”). The OST will suspend program execution until
1024 oscillations are counted. Two-Speed Start-up
mode minimizes the delay in code execution by
operating from the internal oscillator as the OST is
counting. When the OST count reaches 1024 and the
OSTS bit of the OSCCON register is set, program
execution switches to the external oscillator.
2.12.1
TWO-SPEED START-UP MODE
CONFIGURATION
Two-Speed Start-up mode is enabled when all of the
following settings are configured as noted:
Two-Speed Start-up mode is enabled when the
IESO of the CONFIG1H Configuration register is
set.
SCS<1:0> (of the OSCCON register) = 00.
FOSC<2:0> bits of the CONFIG1H Configuration
register are configured for LP, XT or HS mode.
Two-Speed Start-up mode becomes active after:
Power-on Reset (POR) and, if enabled, after
Power-up Timer (PWRT) has expired, or
Wake-up from Sleep.
Note:
Executing a SLEEP instruction will abort
the oscillator start-up time and will cause
the OSTS bit of the OSCCON register to
remain clear.
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