參數(shù)資料
型號(hào): PIC18F65K22-I/MRRSL
廠商: Microchip Technology
文件頁數(shù): 36/61頁
文件大?。?/td> 0K
描述: MCU PIC 32K FLASH MEM XLP 64QFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 40
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 32KB(16K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 2K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
P89V52X2_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 4 May 2009
41 of 57
NXP Semiconductors
P89V52X2
80C51 with 256 B RAM, 192 B data EEPROM
6.16 Code security (CSEC) bits
The code security bits protect against software piracy and prevent the contents of the
ash from being read by unauthorized parties. The code security bits and their effects are
shown in Table 41.
Table 40.
UCFG - User conguration register bit description
Bit
Symbol
Description
7 to 3
-
Reserved
2
ENW
Enable Write. When programmed = 1, forces the WE bit to be set.
1
FX2
Force X2. When programmed = 1, the device is in 6-clock mode.
When erased = 0, the mode depends on the state of the X2 bit in
CKCON.
0
EXTCLK
External Clock. When programmed = 1, disables the XTAL block when
using an external digital clock source.
Table 41.
CSEC - Code security register bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
-
INTEXEC
PROT
Table 42.
CSEC - Code security register bit description
Bit
Symbol
Description
7 to 2
-
Reserved
1
INTEXEC
Internal execution only. When programmed, if the internal address
space is exceeded, the address will rollover into internal space (upper
address bits are ignored) for MOVC and instruction fetches. MOVC will
access the data EEPROM when the address >= FF00H.
0
PROT
Protect. When programmed, prohibits further erasing or programming
of code memory.
MOVC instructions executed from external code
memory are disabled from fetching code bytes from internal
code memory.
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