參數(shù)資料
型號： PIC18F65K90T-I/PTRSL
廠商： Microchip Technology
文件頁數(shù)： 32/110頁
文件大?。?/td> 0K
描述： MCU 8BIT 32K FLASH 64-TQFP
標準包裝： 1,200
系列： PIC® XLP™ 18F
核心處理器： PIC
芯體尺寸： 8-位
速度： 64MHz
連通性： I²C，LIN，SPI，UART/USART
外圍設備： 欠壓檢測/復位，LCD，POR，PWM，WDT
輸入/輸出數(shù)： 53
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 1.8 V ~ 5.5 V
數(shù)據轉換器： A/D 16x12b
振蕩器型： 內部
工作溫度： -40°C ~ 85°C
封裝/外殼： 64-TQFP
包裝： 帶卷 (TR)
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 479
PIC18F47J53 FAMILY
DECFSZ
Decrement f, Skip if 0
Syntax:
DECFSZ f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f) – 1 dest,
skip if result = 0
Status Affected:
None
Encoding:
0010
11da
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DECFSZ
CNT, 1, 1
GOTO
LOOP
CONTINUE
Before Instruction
PC
=
Address (HERE)
After Instruction
CNT
=
CNT – 1
If CNT
=
0;
PC =
Address (CONTINUE)
If CNT
0;
PC =
Address (HERE + 2)
DCFSNZ
Decrement f, Skip if Not 0
Syntax:
DCFSNZ
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f) – 1 dest,
skip if result
0
Status Affected:
None
Encoding:
0100
11da
ffff
Description:
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction which is already fetched is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1(2)
Note:
3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
If skip:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1
Q2
Q3
Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE
DCFSNZ
TEMP, 1, 0
ZERO
:
NZERO
:
Before Instruction
TEMP
=
?
After Instruction
TEMP
=
TEMP – 1,
If TEMP
=
0;
PC
=
Address (ZERO)
If TEMP
0;
PC
=
Address (NZERO)
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