參數(shù)資料
型號: PIC18F6620-I/PT
廠商: Microchip Technology
文件頁數(shù): 87/165頁
文件大?。?/td> 0K
描述: IC MCU FLASH 32KX16 EE 64TQFP
產品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 52
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據轉換器: A/D 12x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
配用: XLT64PT5-ND - SOCKET TRAN ICE 64MQFP/TQFP
AC164319-ND - MODULE SKT MPLAB PM3 64TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 26
2004 Microchip Technology Inc.
2.6.2
OSCILLATOR TRANSITIONS
PIC18FXX20 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
A timing diagram indicating the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-8.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator, operation
resumes. No additional delays are required after the
synchronization cycles.
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), then the transition will take place
after an oscillator start-up time (TOST) has occurred. A
timing diagram, indicating the transition from the
Timer1 oscillator to the main oscillator for HS, XT and
LP modes, is shown in Figure 2-9.
FIGURE 2-9:
TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q2
Q1
Q4
Q3
Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program
PC + 2
PC
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4
Q1
PC + 4
Q1
TSCS
Clock
Counter
System
Q2
Q3
Q4
Q1
TDLY
TT1P
TOSC
2
1
3
4
5678
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program
PC
PC + 2
Note 1: TOST = 1024 TOSC (drawing not to scale).
T1OSI
System Clock
OSC2
TOST
Q1
PC + 6
TT1P
TOSC
TSCS
12
3
4
5
6
7
8
Counter
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