PIC18F6525/6621/8525/8621
DS39612B-page 20
2005 Microchip Technology Inc.
PORTJ is a bidirectional I/O port(6).
RJ0/ALE
RJ0
ALE
—62
I/O
O
ST
TTL
Digital I/O.
External memory address latch enable.
RJ1/OE
RJ1
OE
—61
I/O
O
ST
TTL
Digital I/O.
External memory output enable.
RJ2/WRL
RJ2
WRL
—60
I/O
O
ST
TTL
Digital I/O.
External memory write low control.
RJ3/WRH
RJ3
WRH
—59
I/O
O
ST
TTL
Digital I/O.
External memory write high control.
RJ4/BA0
RJ4
BA0
—39
I/O
O
ST
TTL
Digital I/O.
System bus byte address 0 control.
RJ5/CE
RJ5
CE
—40
I/O
O
ST
TTL
Digital I/O
External memory access indicator.
RJ6/LB
RJ6
LB
—41
I/O
O
ST
TTL
Digital I/O.
External memory low byte select.
RJ7/UB
RJ7
UB
—42
I/O
O
ST
TTL
Digital I/O.
External memory high byte select.
VSS
9, 25,
41, 56
11, 31,
51, 70
P
—
Ground reference for logic and I/O pins.
VDD
10, 26,
38, 57
12, 32,
48, 71
P
—
Positive supply for logic and I/O pins.
AVSS(8)
20
26
P
—
Ground reference for analog modules.
AVDD(8)
19
25
P
—
Positive supply for analog modules.
TABLE 1-2:
PIC18F6525/6621/8525/8621 PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
PIC18F6X2X
PIC18F8X2X
Legend: TTL = TTL compatible input
CMOS = CMOS compatible input or output
ST
= Schmitt Trigger input with CMOS levels
Analog = Analog input
I
= Input
O
= Output
P
= Power
OD
= Open-Drain (no P diode to VDD)
Note 1: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX (CONFIG3H<0>) is not set (all
Program Memory modes except Microcontroller).
2: Default assignment for ECCP2/P2A when CCP2MX is set (all devices).
3: External memory interface functions are only available on PIC18F8525/8621 devices.
4: Default assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is set and for
all PIC18F6525/6621 devices.
5: Alternate assignment for ECCP2/P2A in PIC18F8525/8621 devices when CCP2MX is not set (Microcontroller mode).
6: PORTH and PORTJ (and their multiplexed functions) are only available on PIC18F8525/8621 devices.
7: Alternate assignment for P1B/P1C/P3B/P3C for PIC18F8525/8621 devices when ECCPMX (CONFIG3H<1>) is not set.
8: AVDD must be connected to a positive supply and AVSS must be connected to a ground reference for proper operation of
the part in user or ICSP modes. See parameter D001 for details.
9: RG5 is multiplexed with MCLR and is only available when the MCLR Resets are disabled.