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| 型號(hào)： | PIC18F6627-E/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 48KX16 64TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Asynchronous Stimulus |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 25MHz |
| 連通性： | I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測(cè)/復(fù)位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 54 |
| 程序存儲(chǔ)器容量： | 96KB（48K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 12x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 64-TQFP |
| 包裝： | 托盤 |
PIC18F6627/6722/8627/8722
DS80221C-page 8
2006 Microchip Technology Inc.
24. Module: Timer1 (Asynchronous Counter)
When writing to the TMR1H register, under
specific conditions, it is possible that the TMR1L
register will miss a count while connected to the
external oscillator via the T1OSO and T1OSI pins.
When Timer1 is started, the circuitry looks for a
falling edge before a rising edge can increment the
counter. Writing to the TMR1H register is similar to
starting Timer1; therefore, the former logic stated
applies any time the TMR1H register is written. If
the TMR1H register is not completely written to
during the high pulse of the external clock, then the
TMR1L register will miss a count due to the circuit
operation stated previously. The high pulse of a
32.768 kHz external clock crystal yields a 15.25
μs
window for the write to TMR1H to occur. The
amount of instructions that can be executed within
this window is frequency dependent, as shown in
Work around
Operating Conditions: FOSC
≥ 4 MHz, no wake-ups
from Sleep, Timer1 interrupt enabled, global
interrupts enabled.
show how the TMR1H register can be updated
while the external clock (32.768 kHz) is still on its
high pulse.
The importance of the code examples is that the
bold instructions are executed within the first
15.25
μs high pulse on the external clock after the
Timer1 overflow occurred. This will allow the
TMR1L register to increment correctly.
TABLE 3:
FREQUENCY DEPENDENT
INSTRUCTION EXECUTION
AMOUNTS
EXAMPLE 5:
PIC18 HIGH PRIORITY INTERRUPT SERVICE ROUTINE
EXAMPLE 6:
PIC18 LOW PRIORITY INTERRUPT SERVICE ROUTINE
Note:
These instructions are required based on
the function of the ISR. If the only code in
the ISR is to reload Timer1, then they are
not required, but may be required if
additional code is added.
FOSC
TCY (
μs)
TCY within
15.25
μs
1MHz
4
3.81
2MHz
2
7.63
4MHz
1
15.25
8 MHz
0.5
30.5
16 MHz
0.25
61
20 MHz
0.2
76.25
40 MHz
0.1
152.5
ISR @ 0x0008
; (3-4Tcy), fixed interrupt latency
BRA
HIGHINT
; (2Tcy), go to high priority interrupt routine
HIGHINT
BTFSC
PIR1, TMR1IF
; (1Tcy), did a Timer1 overflow occur?
BSF
TMR1H, 7
; (1Tcy) Yes, reload for a 1 second overflow
RETFIE
FAST
Total = 7-8 TCY (if Timer1 overflow occurred)
ISR @ 0x0018
; (3-4Tcy), fixed interrupt latency
MOVFF
STATUS, STATUS_TEMP
; (2Tcy), save STATUS register
MOVFF
WREG, WREG_TEMP
; (2Tcy), save working register, refer to note 1
MOVFF
BSR, BSR_TEMP
; (2Tcy), save BSR register, refer to note 1
BTFSS
PIR1, TMR1IF
; (2Tcy), did a Timer1 overflow occur?
BRA
EXIT
; No
BSF
TMR1H, 7
; (1Tcy) Yes, reload for a 1 second overflow
EXIT
MOVFF
BSR_TEMP, BSR
;restore BSR register, refer to note 1
MOVFF
WREG_TEMP, WREG
;restore working register, refer to note 1
MOVFF
STATUS_TEMP, STATUS
;restore STATUS register
RETFIE
Total = 12-13 TCY (if Timer1 overflow occurred)
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