參數(shù)資料
型號: PIC18F6627T-E/PT
廠商: Microchip Technology
文件頁數(shù): 4/16頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 48KX16 64TQFP
產品培訓模塊: Asynchronous Stimulus
標準包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據轉換器: A/D 12x10b
振蕩器型: 內部
工作溫度: -40°C ~ 125°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
PIC18F6627/6722/8627/8722
DS80221C-page 12
2006 Microchip Technology Inc.
37. Module: Reset
This version of silicon does not support the func-
tionality described in Note 1 of parameter D002 in
Section 28.1 “DC Characteristics: Supply
Voltage” of the data sheet. The RAM content may
be altered during a Reset event if the following
conditions are met.
Device is accessing RAM.
Asynchronous Reset (i.e., WDT, BOR or MCLR
occurs when a write operation is being
executed (start of a Q4 cycle).
Work around
None.
Date Codes that pertain to this issue:
All engineering and production devices.
38. Module: External Memory Bus
The A<19:16> EMB address lines and Read/Write
control pins (OE, WRH and WRL) are released to
their respective inactive states at the same time,
violating
the
timing
condition
mentioned
in
Figure 28-8 and Figure 28-9 in the Device Data
Sheet. This may result in a peripheral device on
the bus detecting an address change when a write/
read is initiated. The bus capacitance and signal
delay on the address and control lines can affect
the probability of invalid detection.
Work around
Two work arounds are available:
1. Use a latch based on the falling edge of ALE to
hold the A<19:16> signals.
2. Add a delay circuit to extend the valid time for
A<19:16> signals to ensure the address is
valid until read/write signals go inactive.
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