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PIC18F87J11 FAMILY
DS39778B-page 436
Preliminary
2007 Microchip Technology Inc.
F
Fail-Safe Clock Monitor.............................................313, 325
Exiting .......................................................................326
Interrupts in Power-Managed Modes........................326
POR or Wake-up From Sleep...................................326
WDT During Oscillator Failure ..................................325
Fast Register Stack.............................................................67
Firmware Instructions........................................................329
Flash Configuration Words................................................313
Flash Program Memory.......................................................87
Associated Registers ..................................................96
Control Registers ........................................................88
EECON1 and EECON2 ......................................88
TABLAT (Table Latch) Register..........................90
TBLPTR (Table Pointer) Register.......................90
Erase Sequence .........................................................92
Erasing........................................................................92
Operation During Code-Protect ..................................96
Reading.......................................................................91
Table Pointer
Boundaries Based on Operation.........................90
Table Pointer Boundaries ...........................................90
Table Reads and Table Writes ...................................87
Write Sequence ..........................................................93
Write Sequence (Word Programming)........................95
Writing.........................................................................93
Unexpected Termination.....................................96
Write Verify .........................................................96
FSCM. See Fail-Safe Clock Monitor.
G
GOTO................................................................................350
H
Hardware Multiplier...........................................................109
8 x 8 Multiplication Algorithms ..................................109
Operation ..................................................................109
Performance Comparison (table)..............................109
I
I/O Ports............................................................................127
Input Pull-up Configuration .......................................128
Open-Drain Outputs..................................................128
Pin Capabilities .........................................................127
I
2
C Mode (MSSP)
Acknowledge Sequence Timing................................262
Associated Registers ................................................268
Baud Rate Generator................................................255
Bus Collision
During a Repeated Start Condition...................266
During a Stop Condition....................................267
Clock Arbitration........................................................256
Clock Stretching........................................................248
10-Bit Slave Receive Mode (SEN = 1)..............248
10-Bit Slave Transmit Mode..............................248
7-Bit Slave Receive Mode (SEN = 1)................248
7-Bit Slave Transmit Mode................................248
Clock Synchronization and the CKP bit ....................249
Effects of a Reset......................................................263
General Call Address Support ..................................252
I
2
C Clock Rate w/BRG..............................................255
Master Mode............................................................. 253
Operation.......................................................... 254
Reception ......................................................... 259
Repeated Start Condition Timing ..................... 258
Start Condition Timing...................................... 257
Transmission .................................................... 259
Multi-Master Communication, Bus Collision
and Arbitration .................................................. 263
Multi-Master Mode.................................................... 263
Operation.................................................................. 238
Read/Write Bit Information (R/W Bit)................ 238, 241
Registers .................................................................. 233
Serial Clock (RC3/SCKx/SCLx)................................ 241
Slave Mode............................................................... 238
Address Masking Modes
5-Bit.......................................................... 239
7-Bit.......................................................... 240
Addressing........................................................ 238
Reception ......................................................... 241
Transmission .................................................... 241
Sleep Operation........................................................ 263
Stop Condition Timing .............................................. 262
INCF ................................................................................. 350
INCFSZ............................................................................. 351
In-Circuit Debugger........................................................... 327
In-Circuit Serial Programming (ICSP)....................... 313, 327
Indexed Literal Offset Addressing
and Standard PIC18 Instructions.............................. 376
Indexed Literal Offset Mode.............................................. 376
Indirect Addressing............................................................. 82
INFSNZ............................................................................. 351
Initialization Conditions for all Registers....................... 55–60
Instruction Cycle ................................................................. 68
Clocking Scheme........................................................ 68
Flow/Pipelining............................................................ 68
Instruction Set................................................................... 329
ADDLW..................................................................... 335
ADDWF..................................................................... 335
ADDWF (Indexed Literal Offset Mode)..................... 377
ADDWFC.................................................................. 336
ANDLW..................................................................... 336
ANDWF..................................................................... 337
BC............................................................................. 337
BCF .......................................................................... 338
BN............................................................................. 338
BNC.......................................................................... 339
BNN.......................................................................... 339
BNOV ....................................................................... 340
BNZ .......................................................................... 340
BOV.......................................................................... 343
BRA .......................................................................... 341
BSF........................................................................... 341
BSF (Indexed Literal Offset Mode)........................... 377
BTFSC...................................................................... 342
BTFSS...................................................................... 342
BTG .......................................................................... 343
BZ............................................................................. 344
CALL......................................................................... 344
CLRF ........................................................................ 345
CLRWDT .................................................................. 345
COMF....................................................................... 346
CPFSEQ................................................................... 346