參數(shù)資料
型號(hào): PIC18F66K90-I/MRRSL
廠商: Microchip Technology
文件頁數(shù): 45/110頁
文件大小: 0K
描述: MCU PIC 64K FLASH MEM XLP 64QFN
產(chǎn)品培訓(xùn)模塊: 8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 40
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 64MHz
連通性: I²C,LIN,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LCD,POR,PWM,WDT
輸入/輸出數(shù): 53
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 4K x 8
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-VFQFN 裸露焊盤
包裝: 托盤
PIC18F47J53 FAMILY
DS39964B-page 492
Preliminary
2010 Microchip Technology Inc.
RLNCF
Rotate Left f (No Carry)
Syntax:
RLNCF
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f<n>)
dest<n + 1>,
(f<7>)
dest<0>
Status Affected:
N, Z
Encoding:
0100
01da
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the left. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RLNCF
REG, 1, 0
Before Instruction
REG
=
1010 1011
After Instruction
REG
=
0101 0111
register f
RRCF
Rotate Right f through Carry
Syntax:
RRCF
f {,d {,a}}
Operands:
0
f 255
d
[0,1]
a
[0,1]
Operation:
(f<n>)
dest<n – 1>,
(f<0>)
C,
(C)
dest<7>
Status Affected:
C, N, Z
Encoding:
0011
00da
ffff
Description:
The contents of register ‘f’ are rotated
one bit to the right through the Carry
flag. If ‘d’ is ‘0’, the result is placed in W.
If ‘d’ is ‘1’, the result is placed back in
register ‘f’ (default).
If ‘a(chǎn)’ is ‘0’, the Access Bank is selected.
If ‘a(chǎn)’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a(chǎn)’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write to
destination
Example:
RRCF
REG, 0, 0
Before Instruction
REG
=
1110 0110
C=
0
After Instruction
REG
=
1110 0110
W
=
0111 0011
C=
0
C
register f
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