參數(shù)資料
型號(hào): PIC18F8410T-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 226/411頁(yè)
文件大小: 0K
描述: IC PIC MCU FLASH 8KX16 80TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 70
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 帶卷 (TR)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
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2010-2012 Microchip Technology Inc.
DS39977F-page 301
PIC18F66K80 FAMILY
21.4.2
OPERATION
The MSSP module functions are enabled by setting the
MSSP Enable bit, SSPEN (SSPCON1<5>).
The SSPCON1 register allows control of the I2C
operation. Four mode selection bits (SSPCON1<3:0>)
allow one of the following I2C modes to be selected:
I2C Master mode, clock
I2C Slave mode (7-bit address)
I2C Slave mode (10-bit address)
I2C Slave mode (7-bit address) with Start and
Stop bit interrupts enabled
I2C Slave mode (10-bit address) with Start and
Stop bit interrupts enabled
I2C Firmware Controlled Master mode, slave is
Idle
Selection of any I2C mode with the SSPEN bit set
forces the SCL and SDA pins to be open-drain,
provided these pins are programmed as inputs by
setting the appropriate TRISC bit. To ensure proper
operation of the module, pull-up resistors must be
provided externally to the SCL and SDA pins.
21.4.3
SLAVE MODE
In Slave mode, the SCL and SDA pins must be
configured as inputs (TRISC<4:3> set). The MSSP
module will override the input state with the output data
when required (slave-transmitter).
The I2C Slave mode hardware will always generate an
interrupt on an address match. Address masking will
allow the hardware to generate an interrupt for more
than one address (up to 31 in 7-bit addressing and up
to 63 in 10-bit addressing). Through the mode select
bits, the user can also choose to interrupt on Start and
Stop bits.
When an address is matched, or the data transfer after
an address match is received, the hardware auto-
matically will generate the Acknowledge (ACK) pulse
and load the SSPBUF register with the received value
currently in the SSPSR register.
Any combination of the following conditions will cause
the MSSP module not to give this ACK pulse:
The Buffer Full bit, BF (SSPSTAT<0>), was set
before the transfer was received.
The overflow bit, SSPOV (SSPCON1<6>), was
set before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit, SSPIF, is set. The BF bit is
cleared by reading the SSPBUF register, while bit,
SSPOV, is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the
MSSP module, are shown in timing Parameter 100 and
Parameter 101.
21.4.3.1
Addressing
Once the MSSP module has been enabled, it waits for
a Start condition to occur. Following the Start condition,
the 8 bits are shifted into the SSPSR register. All incom-
ing bits are sampled with the rising edge of the clock
(SCL) line. The value of register, SSPSR<7:1>, is com-
pared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match and the BF
and SSPOV bits are clear, the following events occur:
1.
The SSPSR register value is loaded into the
SSPBUF register.
2.
The Buffer Full bit, BF, is set.
3.
An ACK pulse is generated.
4.
The MSSP Interrupt Flag bit, SSPIF, is set (and
interrupt is generated, if enabled) on the falling
edge of the ninth SCL pulse.
In 10-Bit Addressing mode, two address bytes need to
be received by the slave. The five Most Significant bits
(MSbs) of the first address byte specify if this is a 10-bit
address. The R/W (SSPSTAT<2>) bit must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘11110 A9 A8 0’, where ‘A9’ and ‘A8’ are the
two MSbs of the address. The sequence of events for
10-bit addressing is as follows, with Steps 7 through 9
for the slave-transmitter:
1.
Receive first (high) byte of address (bits, SSPIF,
BF and UA, are set on address match).
2.
Update the SSPADD register with second (low)
byte of address (clears bit, UA, and releases the
SCL line).
3.
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
4.
Receive second (low) byte of address (bits,
SSPIF, BF and UA, are set).
5.
Update the SSPADD register with the first (high)
byte of address. If match releases SCL line, this
will clear bit, UA.
6.
Read the SSPBUF register (clears bit, BF) and
clear flag bit SSPIF.
7.
Receive Repeated Start condition.
8.
Receive first (high) byte of address (bits, SSPIF
and BF, are set).
9.
Read the SSPBUF register (clears bit, BF) and
clear flag bit, SSPIF.
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