參數(shù)資料
型號: PIC18F8628-I/PT
廠商: Microchip Technology
文件頁數(shù): 16/60頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 48KX16 80TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 70
程序存儲器容量: 96KB(48K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 644 (CN2011-ZH PDF)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
2009 Microchip Technology Inc.
DS39894B-page 23
PIC18F8723 FAMILY
PORTB is a bidirectional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
RB0/INT0/FLT0
RB0
INT0
FLT0
58
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
PWM Fault input for ECCPx.
RB1/INT1
RB1
INT1
57
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
56
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/INT3/ECCP2/P2A
RB3
INT3
ECCP2(1)
P2A(1)
55
I/O
I
O
TTL
ST
Digital I/O.
External interrupt 3.
Enhanced Capture 2 input/Compare 2 output/
PWM2 output.
ECCP2 PWM output A.
RB4/KBI0
RB4
KBI0
54
I/O
I
TTL
Digital I/O.
Interrupt-on-change pin.
RB5/KBI1/PGM
RB5
KBI1
PGM
53
I/O
I
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
Low-Voltage ICSP Programming enable pin.
RB6/KBI2/PGC
RB6
KBI2
PGC
52
I/O
I
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming clock pin.
RB7/KBI3/PGD
RB7
KBI3
PGD
47
I/O
I
I/O
TTL
ST
Digital I/O.
Interrupt-on-change pin.
In-Circuit Debugger and ICSP programming data pin.
TABLE 1-3:
PIC18F8628/8723 (80-PIN) PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
Description
TQFP
Legend: TTL = TTL compatible input
CMOS
= CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
Analog
= Analog input
I
= Input
O
= Output
P= Power
I2C/SMB = I2C/SMBus input buffer
Note 1: Alternate assignment for ECCP2 when Configuration bit, CCP2MX, is cleared (all operating modes except
Microcontroller mode).
2: Default assignment for ECCP2 in all operating modes (CCP2MX is set).
3: Alternate assignment for ECCP2 when CCP2MX is cleared (Microcontroller mode only).
4: Default assignment for P1B/P1C/P3B/P3C (ECCPMX is set).
5: Alternate assignment for P1B/P1C/P3B/P3C (ECCPMX is clear).
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