參數(shù)資料
型號: PIC18F86J11-I/PT
廠商: Microchip Technology
文件頁數(shù): 59/107頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32KX16 80TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標準包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲器容量: 64KB(32K x 16)
程序存儲器類型: 閃存
RAM 容量: 3930 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 15x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 644 (CN2011-ZH PDF)
配用: AC162091-ND - HEADER MPLAB ICD2 18F87J11 64/80
MA180020-ND - MODULE PLUG-IN HPC EXPL 18F87J11
AC164328-ND - MODULE SKT FOR 80TQFP
2007-2012 Microchip Technology Inc.
DS39778E-page 55
PIC18F87J11 FAMILY
5.0
RESET
The PIC18F87J11 family of devices differentiate
between various kinds of Reset:
a)
Power-on Reset (POR)
b)
MCLR Reset during normal operation
c)
MCLR Reset during power-managed modes
d)
Watchdog Timer (WDT) Reset (during
execution)
e)
Configuration Mismatch (CM)
f)
Brown-out Reset (BOR)
g)
RESET
Instruction
h)
Stack Full Reset
i)
Stack Underflow Reset
This section discusses Resets generated by MCLR,
POR and BOR, and covers the operation of the various
start-up timers. Stack Reset events are covered in
WDT Resets are covered in Section 25.2 “Watchdog
.
A simplified block diagram of the on-chip Reset circuit
is shown in Figure 5-1.
5.1
RCON Register
Device Reset events are tracked through the RCON
register (Register 5-1). The lower five bits of the
register indicate that a specific Reset event has
occurred. In most cases, these bits can only be set by
the event and must be cleared by the application after
the event. The state of these flag bits, taken together,
can be read to indicate the type of Reset that just
occurred. This is described in more detail in
.
The RCON register also has a control bit for setting
interrupt priority (IPEN). Interrupt priority is discussed
FIGURE 5-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External Reset
MCLR
VDD
WDT
Time-out
VDD Rise
Detect
PWRT
INTRC
POR Pulse
Chip_Reset
Brown-out
Reset(1)
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
Sleep
( )_IDLE
32
s
Note 1:
The ENVREG pin must be tied high to enable Brown-out Reset. The Brown-out Reset is provided by the on-chip
voltage regulator when there is insufficient source voltage to maintain regulation.
PWRT
11-Bit Ripple Counter
66 ms
S
R
Q
Configuration Word Mismatch
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