參數(shù)資料
型號(hào): PIC18F86J50-I/PT
廠商: Microchip Technology
文件頁數(shù): 43/61頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32KX16 80TQFP
產(chǎn)品培訓(xùn)模塊: Asynchronous Stimulus
PIC18 J Series MCU Overview
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: EBI/EMI,I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 65
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 12x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 644 (CN2011-ZH PDF)
配用: AC162087-ND - HEADER MPLAB ICD2 18F87J50 68/84
MA180021-ND - MODULE PLUG-IN 18F87J50 FS USB
AC164328-ND - MODULE SKT FOR 80TQFP
Philips Semiconductors
Product data
P87LPC767
Low power, low price, low pin count (20 pin)
microcontroller with 4-kbyte OTP and 8-bit A/D converter
2002 Mar 25
45
SU01635
WATCHDOG
INTERRUPT
S
Q
20-BIT COUNTER
STATE CLOCK
WDTE (UCFG1.7)
BOF (PCON.5)
POF (PCON.4)
WATCHDOG
RESET
CLEAR
8 MSBs
8 TO 1 MUX
WATCHDOG
FEED DETECT
WDOVF
(WDCON.5)
WDS2–0
(WDCON.2–0)
WDTE + WDRUN
WDCLK * WDTE
500 kHz
RC OSCILLATOR
ENABLE
CLOCK OUT
R
Figure 35. Block Diagram of the Watchdog Timer
BIT
SYMBOL
FUNCTION
WDCON.7, 6
Reserved for future use. Should not be set to 1 by user programs.
WDCON.5
WDOVF
Watchdog timer overflow flag. Set when a watchdog reset or timer overflow occurs. Cleared when
the watchdog is fed.
WDCON.4
WDRUN
Watchdog run control. The watchdog timer is started when WDRUN = 1 and stopped when
WDRUN = 0. This bit is forced to 1 (watchdog running) if the WDTE configuration bit = 1.
WDCON.3
WDCLK
Watchdog clock select. The watchdog timer is clocked by CPU clock/6 when WDCLK = 1 and by
the watchdog RC oscillator when WDCLK = 0. This bit is forced to 0 (using the watchdog RC
oscillator) if the WDTE configuration bit = 1.
WDCON.2–0 WDS2–0
Watchdog rate select.
WDS2–0
Timeout Clocks
Minimum Time
Nominal Time
Maximum Time
0 0 0
8,192
10 ms
16 ms
23 ms
0 0 1
16,384
20 ms
32 ms
45 ms
0 1 0
32,768
41 ms
65 ms
90 ms
0 1 1
65,536
82 ms
131 ms
180 ms
1 0 0
131,072
165 ms
262 ms
360 ms
1 0 1
262,144
330 ms
524 ms
719 ms
1 1 0
524,288
660 ms
1.05 sec
1.44 sec
1 1 1
1,048,576
1.3 sec
2.1 sec
2.9 sec
WDS0
SU01183
WDS1
WDS2
WDCLK
WDRUN
WDOVF
0
1
2
3
4
5
6
7
WDCON
Reset Value:
S 30h for a watchdog reset.
S 10h for other rest sources if the watchdog is enabled via the WDTE configuration bit.
S 00h for other reset sources if the watchdog is disabled via the WDTE configuration bit.
Not Bit Addressable
Address: A7h
Figure 36. Watchdog Timer Control Register (WDCON)
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