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參數(shù)資料
| 型號(hào)： | PIC18F86J60-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 3/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 32KX16 80TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Embedded Ethernet Asynchronous Stimulus PIC18 J Series MCU Overview 8-bit PIC® Microcontroller Portfolio |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 41.667MHz |
| 連通性： | 以太網(wǎng)，I²C，SPI，UART/USART |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 55 |
| 程序存儲(chǔ)器容量： | 64KB（32K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 3808 x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 15x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 645 (CN2011-ZH PDF) |
| 配用： | AC162064-ND - HEADER INTFC MPLABICD2 64/80/100 AC164328-ND - MODULE SKT FOR 80TQFP |
2008 Microchip Technology Inc.
DS80292D-page 3
PIC18F97J60 FAMILY
5.
Module: Ethernet (MIIM)
When writing to any PHY register through the MIIM
interface’s MIWRL and MIWRH registers, the low
byte actually written to the PHY register may be
corrupted. The corruption occurs when the
following actions are taken:
The application writes to MIWRL
The PIC MCU core executes any instruction
that reads or writes to any memory address that
has the Least Significant six address bits of 36h
(‘b110110)
The application writes to MIWRH
For example, the following sequence will result in
a corrupted write to a PHY register:
In this example, 0xCF5 and 0xCF6 are GPR
memory locations that the application wishes to
write to the current PHY register defined by the
MIREGADR SFR. When the PIC MCU core
reads from
the
GPR
at
address
0xCF6
(‘b110011110110), the value originally written to
MIWRL will be corrupted.
Work around 1
Ensure that following a write to MIWRL, the firm-
ware does not access any of the problem memory
locations prior to writing to MIWRH. After finished
writing to MIWRH, normal operation can resume.
If interrupts are enabled, disable them prior to writ-
ing to MIWRL and MIWRH to prevent an Interrupt
Service Routine (ISR) from performing any reads
or writes to a problem memory address.
Special care must be taken to ensure that the
source data to be written to MIWRH does not
result in a problem memory access.
The following PHY write sequence avoids the
problem:
1. Copy the low byte, to be written to the PHY, into
the PRODL register.
PRODL is at address FF3h and not subject to
the memory address issue.
2. Copy the high byte, to be written to the PHY,
into the PRODH register.
PRODH is at address FF4h and not subject to
the memory address issue.
3. Disable all interrupts by clearing GIEH and
GIEL in the INTCON register.
4. Move PRODL into MIWRL.
5. Wait one instruction cycle, as required by the
MAC host interface logic.
6. Move PRODH into MIWRH.
7. Enable all interrupts that are needed by
restoring GIEH and GIEL in INTCON.
Work around 2
If you cannot disable interrupts, as specified in
Work around 1, because the application cannot
tolerate interrupt latency variations:
Perform the write (with interrupts enabled), but
Verify the correct values were written by
reading the PHY register
If a corrupted value was written due to an interrupt
occurring, perform the write again and reverify.
The source data must be stored in a non-problem
location.
The
application
should
follow
the
following
procedure:
1. Copy the low byte, to be written to the PHY, into
the PRODL register.
PRODL is at address FF3h and not subject to
the memory address issue.
2. Copy the high byte, to be written to the PHY,
into the PRODH register.
PRODH is at address FF4h and not subject to
the memory address issue.
3. Move PRODL into MIWRL.
4. Wait one instruction cycle, as required by the
MAC host interface logic.
5. Move PRODH into MIWRH.
6. Wait two TCY and then poll the BUSY bit
(MISTAT<0>) until it is clear.
7. Perform a PHY register read of the same
location.
8. Compare the read result with the original value
copied to the PRODH:PRODL registers. If they
do not match, return to step 1.
Date Codes that pertain to this issue:
All engineering and production devices.
6.
Module: Ethernet (RX Filter)
When enabled, the Pattern Match receive filter
may allow some packets with an incorrect data
pattern to be received. Also, in certain configura-
tions, packets with a valid pattern may be
incorrectly discarded.
Work around
Do not use the Pattern Match hardware filter.
Instead, use the Unicast, Mutlicast, Broadcast and
Hash Table receive filters to accept all needed
packets and filter out unwanted ones in software.
Date Codes that pertain to this issue:
All engineering and production devices.
MOVFF
0xCF5, MIWRL
NOP
MOVFF
0xCF6, MIWRH
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