參數(shù)資料
型號: PIC18F8720-I/PT
廠商: Microchip Technology
文件頁數(shù): 158/165頁
文件大?。?/td> 0K
描述: IC MCU FLASH 64KX16 EE 80TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 68
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大?。?/td> 1K x 8
RAM 容量: 3.75K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC174011-ND - MODULE SKT PROMATEII 80TQFP
PIC18F6520/8520/6620/8620/6720/8720
DS39609B-page 90
2004 Microchip Technology Inc.
REGISTER 9-2:
INTCON2 REGISTER
R/W-1
RBPU
INTEDG0
INTEDG1
INTEDG2
INTEDG3
TMR0IP
INT3IP
RBIP
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1
= All PORTB pull-ups are disabled
0
= PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG0: External Interrupt 0 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 5
INTEDG1: External Interrupt 1 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 4
INTEDG2: External Interrupt 2 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 3
INTEDG3: External Interrupt 3 Edge Select bit
1
= Interrupt on rising edge
0
= Interrupt on falling edge
bit 2
TMR0IP: TMR0 Overflow Interrupt Priority bit
1
= High priority
0
= Low priority
bit 1
INT3IP: INT3 External Interrupt Priority bit
1
= High priority
0
= Low priority
bit 0
RBIP: RB Port Change Interrupt Priority bit
1
= High priority
0
= Low priority
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state
of its corresponding enable bit or the global enable bit. User software should ensure
the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature
allows for software polling.
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