參數(shù)資料
型號: PIC18F8723-I/PT
廠商: Microchip Technology
文件頁數(shù): 29/60頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 64KX16 80TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 119
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 70
程序存儲器容量: 128KB(64K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 1K x 8
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 4.2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 80-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 644 (CN2011-ZH PDF)
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
2009 Microchip Technology Inc.
DS39894B-page 35
PIC18F8723 FAMILY
The value in the ADRESH:ADRESL registers is
unknown following Power-on and Brown-out Resets and
is not affected by any other Reset.
After the A/D module has been configured as desired,
the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 2.1
tion time has elapsed, the A/D conversion can be
started. An acquisition time can be programmed to
occur between setting the GO/DONE bit and the actual
start of the conversion.
The following steps should be followed to perform an A/D
conversion:
1.
Configure the A/D module:
Configure analog pins, voltage reference and
digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D acquisition time (ADCON2)
Select A/D conversion clock (ADCON2)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time (if required).
4.
Start conversion:
Set GO/DONE bit (ADCON0<1>)
5.
Wait for A/D conversion to complete by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result registers (ADRESH:ADRESL);
clear bit, ADIF, if required.
7.
For next conversion, go to step 1 or step 2, as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 2-2:
A/D TRANSFER FUNCTION
FIGURE 2-3:
ANALOG INPUT MODEL
Dig
ita
lCo
d
eO
utp
ut
FFEh
003h
002h
001h
000h
0
.5
LS
B
1LS
B
1
.5
LS
B
2LS
B
2
.5
LS
B
40
94
LS
B
4
094
.5
LS
B
3LS
B
Analog Input Voltage
FFFh
40
95
LS
B
4
095
.5
LS
B
VAIN
CPIN
Rs
ANx
5 pF
VT = 0.6V
ILEAKAGE
RIC
≤ 1k
Sampling
Switch
SS
RSS
CHOLD = 25 pF
VSS
VDD
±100 nA
Legend: CPIN
VT
ILEAKAGE
RIC
SS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch
= Sample/Hold Capacitance (from DAC)
various junctions
= Sampling Switch Resistance
RSS
VDD
6V
Sampling Switch
5V
4V
3V
2V
12
3
4
(k
Ω)
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