PIC18F6X2X/8X2X
DS39612A-page 232
Advance Information
2003 Microchip Technology Inc.
19.4
USART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTAx<7>). This mode differs from the Syn-
chronous Master mode in that the shift clock is supplied
externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any Low Power mode.
19.4.1
USART SYNCHRONOUS SLAVE
TRANSMIT
The operation of the Synchronous Master and Slave
modes are identical except in the case of the SLEEP
mode.
If two words are written to the TXREGx and then the
SLEEP
instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit.
b)
The second word will remain in TXREGx
register.
c)
Flag bit TXIF will not be set.
d)
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXIF will now be
set.
e)
If enable bit TXIE is set, the interrupt will wake
the chip from SLEEP. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1.
Enable the synchronous slave serial port by set-
ting bits SYNC and SPEN and clearing bit
CSRC.
2.
Clear bits CREN and SREN.
3.
If interrupts are desired, set enable bit TXIE.
4.
If 9-bit transmission is desired, set bit TX9.
5.
Enable the transmission by setting enable bit
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
7.
Start transmission by loading data to the
TXREGx register.
8.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
PIR1
PIE1
IPR1
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
GIE/GIEH
—
—
—
SPEN
USART Transmit Register
CSRC
—
Baud Rate Generator Register, High Byte
Baud Rate Generator Register, Low Byte
x
= unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
PEIE/GIEL
ADIF
ADIE
ADIP
RX9
TMR0IE
RCIF
RCIE
RCIP
SREN
INT0IE
TXIF
TXIE
TXIP
CREN
RBIE
—
—
—
ADDEN
TMR0IF
CCP1IF
CCP1IE
CCP1IP
FERR
INT0IF
TMR2IF
TMR2IE
TMR2IP
OERR
RBIF
TMR1IF
TMR1IE
TMR1IP
RX9D
0000 000x
0000 000u
-000 -000
-000 -000
-000 -000
-000 -000
-111 -111
-111 -111
0000 -00x
0000 -00x
0000 0000
0000 0000
TX9
RCIDL
TXEN
—
SYNC
SCKP
SENDB
BRG16
BRGH
—
TRMT
WUE
TX9D
ABDEN
0000 0010
0000 0010
-1-1 0-00
-1-1 0-00
0000 0000
0000 0000
0000 0000
0000 0000