參數(shù)資料
型號(hào): PIC18LC601T-I/PT
廠商: Microchip Technology
文件頁(yè)數(shù): 63/319頁(yè)
文件大小: 0K
描述: IC MCU ROMLESS A/D PWM 64TQFP
標(biāo)準(zhǔn)包裝: 1,200
系列: PIC® 18C
核心處理器: PIC
芯體尺寸: 8-位
速度: 25MHz
連通性: EBI/EMI,I²C,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 26
程序存儲(chǔ)器類型: ROMless
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 帶卷 (TR)
其它名稱: PIC18LC601TI/PT
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PIC18F2585/2680/4585/4680
DS39625C-page 154
Preliminary
2007 Microchip Technology Inc.
12.3.3
TIMER1 OSCILLATOR LAYOUT
CONSIDERATIONS
The Timer1 oscillator circuit draws very little power
during operation. Due to the low-power nature of the
oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit, shown in Figure 12-3, should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high-speed circuit must be located near the oscilla-
tor (such as the CCP1 pin in Output Compare or PWM
mode, or the primary oscillator using the OSC2 pin), a
grounded guard ring around the oscillator circuit, as
shown in Figure 12-4, may be helpful when used on a
single-sided PCB or in addition to a ground plane.
FIGURE 12-4:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
12.4
Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is
latched in interrupt
flag
bit, TMR1IF
(PIR1<0>). This interrupt can be enabled or disabled
by setting or clearing the Timer1 Interrupt Enable bit,
TMR1IE (PIE1<0>).
12.5
Resetting Timer1 Using the CCP1
Special Event Trigger
If either of the CCP1 modules is configured in Compare
mode
to
generate
a
special
event
trigger
(CCP1M3:CCP1M0
or
CCP2M3:CCP2M0 = 1011),
this signal will reset Timer1. The trigger from ECCP1
will also start an A/D conversion if the A/D module is
for more information.).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPR1H:CCPR1L register
pair effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger, the write operation will take
precedence.
12.6
Using Timer1 as a Real-Time
Clock
Adding an external LP oscillator to Timer1 (such as the
above) gives users the option to include RTC function-
ality to their applications. This is accomplished with an
inexpensive watch crystal to provide an accurate time
base and several lines of application code to calculate
the time. When operating in Sleep mode and using a
battery or supercapacitor as a power source, it can
completely eliminate the need for a separate RTC
device and battery backup.
The application code routine, RTCisr, shown in
Example 12-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16 bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to pre-
load it. The simplest method is to set the MSb of
TMR1H with a BSF instruction. Note that the TMR1L
register is never preloaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1) as shown in the routine,
RTCinit
. The Timer1 oscillator must also be enabled
and running at all times.
VDD
OSC1
VSS
OSC2
RC0
RC1
RC2
Note: Not drawn to scale.
Note:
The special event triggers from the
ECCP1 module will not set the TMR1IF
interrupt flag bit (PIR1<0>).
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