
PIC18FXX8
DS41159B-page 200
Preliminary
2002 Microchip Technology Inc.
REGISTER 19-2:
CANSTAT – CAN STATUS REGISTER
R-1
R-0
R-0
U-0
—
R-0
R-0
R-0
U-0
—
OPMODE2 OPMODE1 OPMODE0
bit 7
ICODE2
ICODE1
ICODE0
bit 0
bit 7-5
OPMODE2:OPMODE0:
Operation Mode Status bits
111
= Reserved
110
= Reserved
101
= Reserved
100
= Configuration mode
011
= Listen Only mode
010
= Loopback mode
001
= Disable mode
000
= Normal mode
Note:
Before the device goes into SLEEP mode, select Disable mode.
bit 4
bit 3-1
Unimplemented:
Read as ’0’
ICODE2:ICODE0:
Interrupt Code bits
When an interrupt occurs, a prioritized coded interrupt value will be present in the
ICODE3:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE3:ICODE0
bits can be copied to the WIN3:WIN0 bits to select the correct buffer to map into the Access
Bank area. See Example 19-1 for code example.
111
= Wake-up on Interrupt
110
= RXB0 Interrupt
101
= RXB1 Interrupt
100
= TXB0 Interrupt
011
= TXB1 Interrupt
010
= TXB2 Interrupt
001
= Error Interrupt
000
= No Interrupt
Unimplemented:
Read as ’0’
bit 0
Legend:
R = Readable bit
- n = Value at POR
W = Writable bit
’1’ = Bit is set
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
x = Bit is unknown