參數(shù)資料
型號: PIC18LF2520-I/SP
廠商: Microchip Technology
文件頁數(shù): 116/151頁
文件大?。?/td> 0K
描述: IC MCU FLASH 16KX16 28-DIP
產品培訓模塊: Asynchronous Stimulus
標準包裝: 15
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,HLVD,POR,PWM,WDT
輸入/輸出數(shù): 25
程序存儲器容量: 32KB(16K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 1.5K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉換器: A/D 10x10b
振蕩器型: 內部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-DIP(0.300",7.62mm)
包裝: 管件
產品目錄頁面: 643 (CN2011-ZH PDF)
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 383
PIC16(L)F1782/3
TABLE 30-5:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Operating Temperature -40°C
TA +125°C
Param
No.
Sym.
Characteristic
Min.
Typ Max. Units
Conditions
30
TMCLMCLR Pulse Width (low)
2
5
s
VDD = 3.3-5V, -40°C to +85°C
VDD = 3.3-5V
31
TWDTLP Low-Power Watchdog Timer
Time-out Period
10
16
27
ms
VDD = 3.3V-5V
1:16 Prescaler used
32
TOST
Oscillator Start-up Timer Period(1), (2)
1024
Tosc (Note 3)
33*
TPWRT
Power-up Timer Period, PWRTE = 0
40
65
140
ms
34*
TIOZ
I/O high-impedance from MCLR Low
or Watchdog Timer Reset
——
2.0
s
35
VBOR
Brown-out Reset Voltage
2.55
2.30
1.80
2.70
2.45
1.90
2.85
2.6
2.10
V
BORV = 0
BORV=1 (F device)
BORV=1 (LF device)
35A
VLPBOR Low-Power Brown-out
1.8
2.1
2.5
V
LPBOR = 1
36*
VHYST
Brown-out Reset Hysteresis
0
25
75
mV
-40°C to +85°C
37*
TBORDC Brown-out Reset DC Response
Time
135
sVDD VBOR
*
These parameters are characterized but not tested.
Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1:
Instruction cycle period (TCY) equals four times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with the
device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min” values with an external
clock applied to the OSC1 pin. When an external clock input is used, the “max” cycle time limit is “DC” (no
clock) for all devices.
2:
By design.
3:
Period of the slower clock.
4:
To ensure these voltage tolerances, VDD and VSS must be capacitively decoupled as close to the device as
possible. 0.1
F and 0.01 F values in parallel are recommended.
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