參數(shù)資料
型號(hào): PIC18LF26J50-I/SS
廠商: Microchip Technology
文件頁數(shù): 19/32頁
文件大小: 0K
描述: IC PIC MCU FLASH 64K 2V 28-SSOP
產(chǎn)品培訓(xùn)模塊: XLP Deep Sleep Mode
8-bit PIC® Microcontroller Portfolio
標(biāo)準(zhǔn)包裝: 47
系列: PIC® XLP™ 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 48MHz
連通性: I²C,SPI,UART/USART,USB
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 16
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 3.8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-SSOP(0.209",5.30mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 657 (CN2011-ZH PDF)
PIC18F2XJXX/4XJXX FAMILY
DS39687E-page 26
2009 Microchip Technology Inc.
RTCOSC
CONFIG3L
RTCC Reference Clock Select bit
1 = RTCC uses T1OSC/T1CKI as reference clock
0 = RTCC uses INTRC as reference clock
DSWDTOSC
CONFIG3L
DSWDT Reference Clock Select bit
1 = DSWDT uses INTRC as reference clock
0 = DSWDT uses T1OSC/T1CKI as reference clock
MSSPMSK(1,2)
CONFIG3H
MSSP 7-Bit Address Masking Mode Enable bit
1 = 7-Bit Address Masking mode enable
0 = 5-Bit Address Masking mode enable
PLLSEL(5)
CONFIG3H
PLL Selection bit
1 = 4x PLL selected
0 = 96 MHz PLL selected
ADCSEL
CONFIG3H
ADC Mode Selection bit
1 = 10-Bit ADC mode selected
0 = 12-Bit ADC mode selected
IOL1WAY
CONFIG3H
IOLOCK Bit One-Way Set Enable bit
1 = The IOLOCK bit (PPSCON<0>) can be set once, provided the unlock sequence has
been completed. Once set, the Peripheral Pin Select registers cannot be written to a
second time.
0 = The IOLOCK bit (PPSCON<0>) can be set and cleared as needed, provided the
unlock sequence has been completed
WPCFG
CONFIG4L
Write/Erase Protect Configuration Words Page bit (valid when WPDIS = 0)
1 = Configuration Words page is not erase/write-protected unless WPEND and
WPFP<6:0> settings include the Configuration Words page
0 = Configuration Words page is erase/write-protected, regardless of WPEND and
WPFP<6:0>
CONFIG4L
Write/Erase Protect Page Start/End Location bits
Used with WPEND bit to define which pages in Flash will be write/erase-protected.
WPEND
CONFIG4H
Write/Erase Protect Region Select bit (valid when WPDIS = 0)
1 = Flash pages, WPFP<6:0> to Configuration Words page, are write/erase-protected
0 = Flash pages, 0 to WPFP<6:0> are write/erase-protected
WPDIS
CONFIG4H
Write Protect Disable bit
1 = WPFP<6:0>, WPEND and WPCFG bits ignored; all Flash memory may be erased or
written
0 = WPFP<6:0>, WPEND and WPCFG bits enabled; write/erase-protect active for the
selected region(s)
LS48MHZ(3)
CONFIG4H
System Clock Selection bit
1 = System clock is expected at 48 MHz, FS/LS USB CLKEN’s divide-by is set to 8
0 = System clock is expected at 24 MHz, FS/LS USB CLKEN’s divide-by is set to 4
DEV<2:0>
DEVID1
Device ID bits
Used with the DEV<10:3> bits in the Device ID Register 2 to identify the part number.
REV<4:0>
DEVID1
Revision ID bits
Indicate the device revision.
DEV<10:3>
DEVID2
Device ID bits
Used with the DEV<2:0> bits in the Device ID Register 1 to identify the part number.
TABLE 5-7:
PIC18F47J13 AND PIC18F47J53 FAMILY DEVICES: BIT DESCRIPTIONS (CONTINUED)
Bit Name
Configuration
Words
Description
Note 1: The Configuration bits can only be programmed indirectly by programming the Flash Configuration Word.
2: The Configuration bits are reset to ‘1’ only on VDD Reset; it is reloaded with the programmed value at any device Reset.
3: These bits are not implemented in PIC18F47J13 family devices.
4: Once this bit is cleared, all the Configuration registers which reside in the last page are also protected. To disable code
protection, perform an ICSP Bulk Erase operation.
5: Not implemented on PIC18F47J53 family devices.
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PIC18LF26J53-I/ML 功能描述:8位微控制器 -MCU 64KB Flash 4KB RAM 12MIPS nanoWatt RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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