參數(shù)資料
型號: PIC18LF442-I/PT
廠商: Microchip Technology
文件頁數(shù): 114/134頁
文件大?。?/td> 0K
描述: IC MCU FLASH 8KX16 A/D 44TQFP
產(chǎn)品培訓模塊: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
標準包裝: 160
系列: PIC® 18F
核心處理器: PIC
芯體尺寸: 8-位
速度: 40MHz
連通性: I²C,SPI,UART/USART
外圍設備: 欠壓檢測/復位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 34
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
EEPROM 大小: 256 x 8
RAM 容量: 768 x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 5.5 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 44-TQFP
包裝: 托盤
PIC16C9XX
DS30444E - page 80
1997 Microchip Technology Inc.
FIGURE 12-2: ADCON1 REGISTER (ADDRESS 9Fh)
U-0
R/W-0
PCFG2
PCFG1
PCFG0
R = Readable bit
W = Writable bit
U = Unimplemented
bit, read as ‘0’
- n = Value at POR reset
bit7
bit0
bit 7-3:
Unimplemented: Read as '0'
bit 2-0:
PCFG2:PCFG0: A/D Port Conguration Control bits
A = Analog input
D = Digital I/O
PCFG2:PCFG0
RA0
RA1
RA2
RA5
RA3
VREF
000
A
AVDD
001
A
VREF
RA3
010
A
AVDD
011
A
VREF
RA3
100
A
D
A
AVDD
111
D
The ADRES register contains the result of the A/D con-
version. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt ag bit
ADIF is set. The block diagram of the A/D module is
shown in Figure 12-3.
After the A/D module has been congured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine acquisition time, see Section 12.1.
After this acquisition time has elapsed the A/D conver-
sion can be started. The following steps should be fol-
lowed for doing an A/D conversion:
1.
Congure the A/D module:
Congure analog pins / voltage reference /
and digital I/O (ADCON1)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2.
Congure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time.
4.
Start conversion:
Set GO/DONE bit (ADCON0)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result register (ADRES), clear bit
ADIF if required.
7.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
dened as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
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