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參數(shù)資料
| 型號： | PIC18LF8723-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 64KX16 80TQFP |
| 產(chǎn)品培訓模塊： | Asynchronous Stimulus 8-bit PIC® Microcontroller Portfolio |
| 標準包裝： | 119 |
| 系列： | PIC® 18F |
| 核心處理器： | PIC |
| 芯體尺寸： | 8-位 |
| 速度： | 40MHz |
| 連通性： | EBI/EMI，I²C，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，HLVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 70 |
| 程序存儲器容量： | 128KB（64K x 16） |
| 程序存儲器類型： | 閃存 |
| EEPROM 大?。?/td> | 1K x 8 |
| RAM 容量： | 3.8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 5.5 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 80-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 644 (CN2011-ZH PDF) |
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PIC18F8723 FAMILY
DS39894B-page 38
2009 Microchip Technology Inc.
2.4
Operation in Power-Managed
Modes
The selection of the automatic acquisition time and A/D
conversion clock is determined in part by the clock
source and frequency while in a power-managed mode.
If the A/D is expected to operate while the device is in
a power-managed mode, the ADCS2:ADCS0 bits in
ADCON2 should be updated in accordance with the
clock source to be used. The ACQT2:ACQT0 bits do
not need to be adjusted as the ADCS2:ADCS0 bits
adjust the TAD time for the new clock speed. After enter-
ing the mode, an A/D acquisition or conversion may be
started. Once started, the device should continue to be
clocked by the same clock source until the conversion
has been completed.
If desired, the device may be placed into the
corresponding Idle mode during the conversion. If the
device clock frequency is less than 1 MHz, the A/D RC
clock source should be selected.
Operation in Sleep mode requires the A/D FRC clock to
be selected. If the ACQT2:ACQT0 bits are set to ‘000’
and a conversion is started, the conversion will be
delayed one instruction cycle to allow execution of the
SLEEP instruction and entry to Sleep mode. The IDLEN
bit (OSCCON<7>) must have already been cleared
prior to starting the conversion.
2.5
Configuring Analog Port Pins
The ADCON1, TRISA, TRISF and TRISH registers all
configure the A/D port pins. The port pins needed as
analog inputs must have their corresponding TRIS bits
set (input). If the TRIS bit is cleared (output), the digital
output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS3:CHS0 bits and the TRIS bits.
Note 1: When reading the PORT register, all pins
configured as analog input channels will
read as cleared (a low level). Analog con-
version on pins configured as digital pins
can be performed. The voltage on the pin
will be accurately converted.
2: Analog levels on any pin defined as a dig-
ital input may cause the digital input buffer
to consume current out of the device’s
specification limits.
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