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參數(shù)資料
| 型號： | PIC24FJ128GB110-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | PIC® 24F |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 32MHz |
| 連通性： | I²C，SPI，UART/USART，USB OTG |
| 外圍設(shè)備： | 欠壓檢測/復(fù)位，LVD，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 83 |
| 程序存儲器容量： | 128KB（43K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 16K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 2 V ~ 3.6 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x10b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 648 (CN2011-ZH PDF) |
| 配用： | 876-1004-ND - PIC24 BREAKOUT BOARD DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU MA240014-ND - MODULE PLUG-IN PIC24 |
PIC24FJ256GB110 FAMILY
DS80369N-page 2
2008-2011 Microchip Technology Inc.
TABLE 2:
SILICON ISSUE SUMMARY
Module
Feature
Item
Number
Issue Summary
Affected
Revisions(1)
A3
A5
A6
Core
RAM Operation
Repeated register operations entering Doze mode.
X
Core
BOR
Spontaneous BOR with analog or USB peripherals.
X
JTAG
Device
Programming
Programming lockout during JTAG programming.
X
UART
—
Framing issues when using two Stop bits.
X
I/O
PORTB
RB5 remains in high-impedance in Open-Drain mode.
X
SPI
Master mode
SPIxIF and SPIRBF may be set early in some
instances.
X
CTMU
—
Trigger to IC or OC modules may not work.
X
USB
—
Issue with Host mode, low-speed operation.
X
USB
VUSB Regulator
Does not regulate to 3.3V.
X
USB
—
CRC errors while using external transceiver.
X
USB
—
ACTIVIF flag functions only during Sleep.
X
UART
UERIF
Interrupt
Interrupt may not function with multiple errors.
X
UART
FIFO Error
PERR and FERR flags may be incorrect in certain
cases.
X
UART
IrDA
Payload error in 8-bit mode.
X
UART
IrDA
Framing error in 9-bit mode.
X
UART
IrDA
Payload errors in 8-bit mode.
X
I2C
Module
Master mode
Master module may Acknowledge its own
transmission as a slave.
X
I2C
Module
Slave mode
Module may not respond correctly to reserved
addresses.
X
Memory
PSV
False address error traps.
X
ICSP
—
PGEC3/PGED3 not functional.
X
Core
Instruction Set
Issue with Read-After-Write stalls in REPEAT loops.
X
RTCC
—
Unexpected decrements of Alarm Repeat Counter.
X
SPI
Enhanced
Buffer mode
Issue with early full buffer interrupt.
X
A/D
—
Disabled voltage references during Debug mode
(64-pin devices only).
X
SPI
Enhanced
Buffer mode
Issue with SRMPT bit becoming set early in certain
cases.
X
Core
Code-Protect
GCP disables write access to interrupt vectors.
X
CTMU
A/D Trigger
Automatic conversion may not function.
X
Oscillator
LPRC
Failure to restart following BOR events.
X
Oscillator
Two-Speed
Start-up
Feature is not functional.
X
Output
Compare
—
Single missed compare events under certain
conditions.
X
Interrupts
INTx
External interrupts missed when writing to INTCON2.
X
A/D
Converter
—
Module continues to draw current when disabled.
X
Note 1:
Only those issues indicated in the last column apply to the current silicon revision.
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