參數(shù)資料
型號(hào): PIC24FJ256GA110-I/PT
廠商: Microchip Technology
文件頁數(shù): 2/18頁
文件大小: 0K
描述: IC PIC MCU FLASH 256K 100TQFP
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 119
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 85
程序存儲(chǔ)器容量: 256KB(85.5K x 24)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 16K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-TQFP
包裝: 托盤
產(chǎn)品目錄頁面: 648 (CN2011-ZH PDF)
配用: 876-1004-ND - PIC24 BREAKOUT BOARD
MA240015-ND - BOARD MCV PIM FOR 24F256GA
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC164333-ND - MODULE SKT FOR PM3 100QFP
PIC24FJ256GA110 FAMILY
DS80368L-page 10
2008-2011 Microchip Technology Inc.
27. Module: Interrupts (INTx)
Writing to the INTCON2 register may cause an
external interrupt event (inputs on INT0 through
INT4) to be missed. This only happens when the
interrupt event and the write event occur during
the same clock cycle.
Work around
If possible, do not write to INTCON2 while any of
the external interrupts are enabled.
If this cannot be avoided, write the data intended
for INTCON2 to any other register in the inter-
rupt block of the SFR (addresses, 0080h to
00E0h); then write the data to INTCON2.
Be certain to write the data to a register not
being actively used by the application, or to any
of the interrupt flag registers, in order to avoid
spurious interrupts. For example, if the inter-
rupts controlled by IEC5 are not being used in
the application, the code sequence would be:
IEC5 = 0x1E;
INTCON2 = 0x1E;
IEC5 = 0;
It is the user’s responsibility to determine an
appropriate register for the particular application.
Affected Silicon Revisions
28. Module: A/D Converter
Once
the
A/D
module
is
enabled
(AD1CON1<15> = 1), it may continue to draw
extra current even if the module is later disabled
(AD1CON1<15> = 0).
Work around
In addition to disabling the module through the
ADON bit, set the corresponding PMD bit
(ADC1MD,
PMD1<0>)
to
power
it
down
completely.
Disabling the A/D module through the PMD regis-
ter also disables the AD1PCFG registers, which in
turn, affects the state of any port pins with analog
inputs. Users should consider the effect on I/O
ports and other digital peripherals on those ports
when ADC1MD is used for power conservation.
Affected Silicon Revisions
29. Module: CTMU
Using the CTMUMD bit (PMD4<2>) to selec-
tively power down the module may reduce the
accuracy of the internal band gap reference
(VBG). In those cases where VBG is used as a
reference for other analog modules, the accu-
racy of measurements or comparisons may be
affected.
Work around
If the A/D Converter or comparators are being
used with VBG selected as a reference, do not set
the CTMUMD bit.
Affected Silicon Revisions
30. Module: Oscillator
The POSCEN bit (OSCCON<2>) has no effect
when a Primary Oscillator with PLL mode is
selected (COSC<2:0> = 011). If XTPLL, HSPLL
or ECPLL Oscillator mode are selected, and the
device enters Sleep mode, the Primary Oscilla-
tor will be disabled, regardless of the state of the
POSCEN bit.
XT, HS and EC Oscillator modes (without the
PLL) will continue to operate as expected.
Work around
None.
Affected Silicon Revisions
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
A3
A5
A6
XX
X
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