參數(shù)資料
型號: PIC24FJ32GA004-E/ML
廠商: Microchip Technology
文件頁數(shù): 21/52頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 32K 44-QFN
特色產(chǎn)品: PIC24FJ/33FJ MCUs & dsPIC? DSCs
標(biāo)準(zhǔn)包裝: 45
系列: PIC® 24F
核心處理器: PIC
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,LVD,POR,PWM,WDT
輸入/輸出數(shù): 35
程序存儲器容量: 32KB(11K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 2 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 13x10b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 125°C
封裝/外殼: 44-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 647 (CN2011-ZH PDF)
配用: 876-1004-ND - PIC24 BREAKOUT BOARD
DM240011-ND - KIT STARTER MPLAB FOR PIC24F MCU
AC162088-ND - HEADER MPLAB ICD2 24FJ64GA004 28
AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
PIC24FJXXXGA0XX
DS39768D-page 28
2008 Microchip Technology Inc.
FIGURE 4-2:
CONFIRMING PRESENCE
OF PROGRAMMING
EXECUTIVE
4.3
Entering Enhanced ICSP Mode
As shown in Figure 4-3, entering Enhanced ICSP
Program/Verify mode requires three steps:
1.
The MCLR pin is briefly driven high, then low.
2.
A 32-bit key sequence is clocked into PGDx.
3.
MCLR is then driven high within a specified
period of time and held.
The programming voltage applied to MCLR is VIH,
which
is
essentially
VDD
in
the
case
of
PIC24FJXXXGA0XX devices. There is no minimum
time requirement for holding at VIH. After VIH is
removed, an interval of at least P18 must elapse before
presenting the key sequence on PGDx.
The key sequence is a specific 32-bit pattern:
‘0100 1101 0100 0011 0100 1000 0101 0000’
(more easily remembered as 4D434850h in hexa-
decimal format). The device will enter Program/Verify
mode only if the key sequence is valid. The Most
Significant bit (MSb) of the most significant nibble must
be shifted in first.
Once the key sequence is complete, VIH must be
applied to MCLR and held at that level for as long as
Program/Verify mode is to be maintained. An interval of
at least time P19 and P7 must elapse before presenting
data on PGDx. Signals appearing on PGDx before P7
has elapsed will not be interpreted as valid.
On successful entry, the program memory can be
accessed and programmed in serial fashion. While in
the Program/Verify mode, all unused I/Os are placed in
the high-impedance state.
FIGURE 4-3:
ENTERING ENHANCED ICSP MODE
Is
Start
Enter ICSP Mode
Application ID
BBh?
Resident in Memory
Yes
No
Prog. Executive is
Application ID
Read the
be Programmed
Prog. Executive must
from Address
807F0h
Finish
MCLR
PGDx
PGCx
VDD
P6
P14
b31
b30
b29
b28
b27
b2
b1
b0
b3
...
Program/Verify Entry Code = 4D434850h
P1A
P1B
P18
P19
01
00
1
0
P7
VIH
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