參數(shù)資料
型號: PIC24HJ128GP502-I/MM
廠商: Microchip Technology
文件頁數(shù): 11/84頁
文件大?。?/td> 0K
描述: IC PIC MCU FLASH 128K 28QFN-S
標(biāo)準包裝: 61
系列: PIC® 24H
核心處理器: PIC
芯體尺寸: 16-位
速度: 40 MIP
連通性: CAN,I²C,IrDA,LIN,PMP,SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,DMA,POR,PWM,WDT
輸入/輸出數(shù): 21
程序存儲器容量: 128KB(43K x 24)
程序存儲器類型: 閃存
RAM 容量: 8K x 8
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x10b/12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 28-VQFN 裸露焊盤
包裝: 管件
產(chǎn)品目錄頁面: 649 (CN2011-ZH PDF)
配用: AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
2010 Microchip Technology Inc.
DS70152H-page 19
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
TABLE 3-10:
dsPIC33FJ32GS406/606/608/610 AND dsPIC33FJ64GS406/606/608/610
DEVICE CONFIGURATION REGISTER MAP
TABLE 3-9:
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000 FBS
RBS<1:0>
BSS<2:0>
BWRP
0xF80002 FSS(1)
RSS<1:0>
SSS<2:0>
SWRP
0xF80004 FGS
GSS<1:0>
GWRP
0xF80006 FOSCSEL
IESO
—FNOSC<2:0>
0xF80008 FOSC
FCKSM<1:0>
IOL1WAY
OSCIOFNC POSCMD<1:0>
0xF8000A FWDT
FWDTEN WINDIS
WDTPRE
WDTPOST<3:0>
0xF8000C FPOR
PWMPIN
HPOL
LPOL
ALTI2C
—FPWRT<2:0>
0xF8000E FICD
Reserved(2)
JTAGEN(3)
—ICS<1:0>
0xF80010 FUID0
User Unit ID Byte 0
0xF80012 FUID1
User Unit ID Byte 1
0xF80014 FUID2
User Unit ID Byte 2
0xF80016 FUID3
User Unit ID Byte 3
Legend: — = unimplemented bit, read as ‘0’.
Note 1: This Configuration register is not available and reads as 0xFF on dsPIC33FJ32MC302/304 devices.
2: These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
3: The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000 FBS
BSS<2:0>
BWRP
0xF80004 FGS
GSS<1:0>
GWRP
0xF80006 FOSCSEL
IESO
—FNOSC<2:0>
0xF80008 FOSC
FCKSM<1:0>
OSCIOFNC POSCMD<1:0>
0xF8000A FWDT
FWDTEN
WINDIS
WDTPRE
WDTPOST<3:0>
0xF8000C FPOR
ALTQIO
ALTSS1
—FPWRT<2:0>
0xF8000E FICD
Reserved(1)
JTAGEN(2)
—ICS<1:0>
0xF80010 FCMP
CMMPOL1(3)
HYST1<1:0>(3)
CMPPOL0(3) HYST0<1:0>(3)
Legend: — = unimplemented bit, read as ‘0’.
Note 1: These bits are reserved (read as ‘1’) and must be programmed as ‘1’.
2: The JTAGEN bit is set to ‘1’ by factory default. Microchip programmers such as MPLAB ICD 2 and REAL
ICE in-circuit emulator clear this bit by default when connecting to a device.
3: These bits are reserved on dsPIC33FJXXXGS406 devices and always read as ‘1’.
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