參數(shù)資料
型號(hào)： PIC24HJ12GP202-I/ML
廠商： Microchip Technology
文件頁(yè)數(shù)： 183/262頁(yè)
文件大?。?/td> 0K
描述： IC PIC MCU FLASH 12KB 28QFN
產(chǎn)品培訓(xùn)模塊： Graphics LCD System and PIC24 Interface
Asynchronous Stimulus
標(biāo)準(zhǔn)包裝： 61
系列： PIC® 24H
核心處理器： PIC
芯體尺寸： 16-位
速度： 40 MIP
連通性： I²C，SPI，UART/USART
外圍設(shè)備： 欠壓檢測(cè)/復(fù)位，POR，PWM，WDT
輸入/輸出數(shù)： 21
程序存儲(chǔ)器容量： 12KB（4K x 24）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 10x10b/12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 28-VQFN 裸露焊盤
包裝： 管件
產(chǎn)品目錄頁(yè)面： 648 (CN2011-ZH PDF)
配用： AC164336-ND - MODULE SOCKET FOR PM3 28/44QFN
DV164033-ND - KIT START EXPLORER 16 MPLAB ICD2
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2007-2011 Microchip Technology Inc.
DS70282E-page 27
PIC24HJ12GP201/202
4.2
Data Address Space
The PIC24HJ12GP201/202 CPU has a separate 16-
bit-wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. The data
memory maps is shown in Figure 4-3.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
).
PIC24HJ12GP201/202 devices implement up to
1 Kbyte of data memory. Should an EA point to a loca-
tion outside of this area, an all-zero word or byte will be
returned.
4.2.1
DATA SPACE WIDTH
The data memory space is organized in byte address-
able, 16-bit-wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC devices
and improve data space memory usage efficiency, the
PIC24HJ12GP201/202 instruction set supports both
word and byte operations. As a consequence of byte
accessibility, all effective address calculations are inter-
nally scaled to step through word-aligned memory. For
example, the core recognizes that Post-Modified
Register Indirect Addressing mode [Ws++] will result in
a value of Ws + 1 for byte operations and Ws + 2 for
word operations.
Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decoding
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera-
tions, or translating from 8-bit MCU code. If a mis-
aligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction in progress is completed. If the instruction
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe-
cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.
All byte loads into any W register are loaded into the
LSB. The MSB is not modified.
A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternately, for 16-bit unsigned data, user appli-
cations can clear the MSB of any W register by execut-
ing a zero-extend (ZE) instruction on the appropriate
address.
4.2.3
SFR SPACE
The first 2 Kbytes of the near data space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers
(SFRs).
These
are
used
by
the
PIC24HJ12GP201/202 core and peripheral modules
for controlling the operation of the device.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A complete listing of implemented
SFRs, including their addresses, is shown in Table 4-1
through Table 4-21.
4.2.4
NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV
class of instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode with a working register
as an address pointer.
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and pin-
out diagrams for device-specific
information.
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