- 您現在的位置：買賣IC網 > PDF目錄3825 > PIC24HJ64GP210A-I/PT (Microchip Technology)IC PIC MCU FLASH 64KB 100-TQFP PDF資料下載
參數資料
| 型號： | PIC24HJ64GP210A-I/PT |
| 廠商： | Microchip Technology |
| 文件頁數： | 31/84頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PIC MCU FLASH 64KB 100-TQFP |
| 標準包裝： | 119 |
| 系列： | PIC® 24H |
| 核心處理器： | PIC |
| 芯體尺寸： | 16-位 |
| 速度： | 40 MIP |
| 連通性： | I²C，IrDA，LIN，SPI，UART/USART |
| 外圍設備： | 欠壓檢測/復位，DMA，POR，PWM，WDT |
| 輸入/輸出數： | 85 |
| 程序存儲器容量： | 64KB（22K x 24） |
| 程序存儲器類型： | 閃存 |
| RAM 容量： | 8K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 數據轉換器： | A/D 32x10b/12b |
| 振蕩器型： | 內部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 100-TQFP |
| 包裝： | 托盤 |
| 產品目錄頁面： | 648 (CN2011-ZH PDF) |
| 配用： | 876-1004-ND - PIC24 BREAKOUT BOARD |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁
2010 Microchip Technology Inc.
DS70152H-page 37
dsPIC33F/PIC24H PROGRAMMING SPECIFICATION
5.5
Erasing Program Memory
The procedure for erasing program memory (all of code
memory, data memory, executive memory and
code-protect bits) consists of setting NVMCON to
0x404F and then executing the programming cycle. For
segment erase operations, the NVMCON value should
be modified suitably, according to Table 5-2.
Figure 5-6 illustrates the ICSP programming process
for Bulk Erasing program memory. This process
includes the ICSP command code, which must be
transmitted (for each instruction) Least Significant bit
first, using the PGCx and PGDx pins (see Figure 5-2).
FIGURE 5-6:
BULK ERASE FLOW
If a Segment Erase operation is required, Step 3 must
be modified with the appropriate NVMCON value as
per Table 5-2.
The ability to individually erase various segments is a
critical component of the CodeGuard Security
features on dsPIC33F/PIC24H devices. An individual
code segment may be erased without affecting other
segments. In addition, the Configuration register
corresponding to the erased code segment also gets
erased. For example, the user may want to erase the
code in the General Segment without erasing
a bootloader located in the Boot Segment.
The Secure Segment Erase command is used to erase
the Secure Segment and the FSS Configuration
register. The General Segment Erase command is
used to erase the General Segment and the FGS
Configuration register. This command is only effective
if a Boot Segment or Secure Segment has been
enabled.
Before performing any segment erase operation, the
programmer must first determine if the dsPIC33F/
PIC24H device has defined a Boot Segment or Secure
Segment, and ensure that a segment does not get
overwritten by operations on any other segment.
The BSS bit field in the FBS Configuration register can
be read to determine whether a Boot Segment has
been defined. If a Boot Segment has already been
defined (and probably already been programmed), the
user must be warned about this fact. Similarly, the SSS
bit field in the FSS Configuration register can be read
to determine whether a Secure Segment has been
defined. If a Secure Segment has already been defined
(and probably already been programmed), the user
must be warned about this fact.
A Bulk Erase operation is the recommended
mechanism to allow a user to overwrite the Boot
Segment (if one chooses to do so).
In
general,
the
segments
and
CodeGuard
Security-related Configuration registers should be
programmed in the following order:
FBS and Boot Segment
FSS and Secure Segment
FGS and General Segment
Note:
Program memory must be erased before
writing any data to program memory.
Start
End
Set the WR bit to Initiate Erase
Write 0x404F to NVMCON SFR
Delay P11 + P10 Time
Note 1: The
Boot
Segment
and
FBS
Configuration register can only be erased
using a Bulk Erase.
2: A Secure Segment Erase operation also
erases the General Segment and FGS
Configuration register. This is true even if
Secure Segment is present on a device
but not enabled.
相關PDF資料 |
PDF描述 |
|---|---|
| PIC18F4550-I/P | IC PIC MCU FLASH 16KX16 40DIP |
| AT32UC3L064-D3UR | MCU AVR32 64KB FLASH 48TLLGA |
| 516-020-000-102 | CONN PLUG 20POS RACK & PANEL |
| AT32UC3L032-D3UR | MCU AVR32 32KB FLASH 48TLLGA |
| 516-090-000-302 | CONN RACK & PANEL PLUG 90POS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| PIC24HJ64GP210AT-I/PF | 功能描述:16位微控制器 - MCU 16 Bit MCU 40MIPS 64KB FLASH RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| PIC24HJ64GP210AT-I/PT | 功能描述:16位微控制器 - MCU 16 Bit MCU 40MIPS 64KB FLASH RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| PIC24HJ64GP210-E/PF | 功能描述:16位微控制器 - MCU 16B MCU 100LD 40MIPS 64KB FLASH RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| PIC24HJ64GP210-E/PT | 功能描述:16位微控制器 - MCU 16B MCU 40MIPS 64KB FLASH RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
| PIC24HJ64GP210-I/PF | 功能描述:16位微控制器 - MCU 40MIPS 64KB FL RoHS:否 制造商:Texas Instruments 核心:RISC 處理器系列:MSP430FR572x 數據總線寬度:16 bit 最大時鐘頻率:24 MHz 程序存儲器大小:8 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:VQFN-40 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。